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Merge tag 'amd-drm-next-5.18-2022-03-18' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.18-2022-03-18: amdgpu: - Aldebaran fixes - SMU 13.0.5 fixes - DCN 3.1.5 fixes - DCN 3.1.6 fixes - Pipe split fixes - More display FP cleanup - DP 2.0 UHBR fix - DC GPU reset fix - DC deep color ratio fix - SMU robustness fixes - Runtime PM fix for APUs - IGT reload fixes - SR-IOV fix - Misc fixes and cleanups amdkfd: - CRIU fixes - SVM fixes UAPI: - Properly handle SDMA transfers with CRIU Proposed user mode change: checkpoint-restore/criu#1709 Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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drivers/gpu/drm/amd/amdgpu/Makefile

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -53,11 +53,11 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
5353
amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
5454
amdgpu_gtt_mgr.o amdgpu_preempt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o \
5555
amdgpu_atomfirmware.o amdgpu_vf_error.o amdgpu_sched.o \
56-
amdgpu_debugfs.o amdgpu_ids.o amdgpu_gmc.o amdgpu_mmhub.o \
56+
amdgpu_debugfs.o amdgpu_ids.o amdgpu_gmc.o \
5757
amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
5858
amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
5959
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
60-
amdgpu_fw_attestation.o amdgpu_securedisplay.o amdgpu_hdp.o \
60+
amdgpu_fw_attestation.o amdgpu_securedisplay.o \
6161
amdgpu_eeprom.o amdgpu_mca.o
6262

6363
amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -626,7 +626,7 @@ amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
626626
if (mode->type & DRM_MODE_TYPE_PREFERRED) {
627627
if (mode->hdisplay != native_mode->hdisplay ||
628628
mode->vdisplay != native_mode->vdisplay)
629-
memcpy(native_mode, mode, sizeof(*mode));
629+
drm_mode_copy(native_mode, mode);
630630
}
631631
}
632632

@@ -635,7 +635,7 @@ amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
635635
list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
636636
if (mode->hdisplay == native_mode->hdisplay &&
637637
mode->vdisplay == native_mode->vdisplay) {
638-
*native_mode = *mode;
638+
drm_mode_copy(native_mode, mode);
639639
drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
640640
DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
641641
break;

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -340,7 +340,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
340340
if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
341341
s64 min_us;
342342

343-
/* Be more aggresive on dGPUs. Try to fill a portion of free
343+
/* Be more aggressive on dGPUs. Try to fill a portion of free
344344
* VRAM now.
345345
*/
346346
if (!(adev->flags & AMD_IS_APU))
@@ -1280,7 +1280,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
12801280
continue;
12811281

12821282
/*
1283-
* Work around dma_resv shortcommings by wrapping up the
1283+
* Work around dma_resv shortcomings by wrapping up the
12841284
* submission in a dma_fence_chain and add it as exclusive
12851285
* fence.
12861286
*/

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 13 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2159,8 +2159,10 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
21592159
!pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
21602160
adev->flags |= AMD_IS_PX;
21612161

2162-
parent = pci_upstream_bridge(adev->pdev);
2163-
adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2162+
if (!(adev->flags & AMD_IS_APU)) {
2163+
parent = pci_upstream_bridge(adev->pdev);
2164+
adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2165+
}
21642166

21652167
amdgpu_amdkfd_device_probe(adev);
21662168

@@ -3664,6 +3666,15 @@ int amdgpu_device_init(struct amdgpu_device *adev,
36643666
if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
36653667
adev->enable_mes = true;
36663668

3669+
/*
3670+
* Reset domain needs to be present early, before XGMI hive discovered
3671+
* (if any) and intitialized to use reset sem and in_gpu reset flag
3672+
* early on during init and before calling to RREG32.
3673+
*/
3674+
adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");
3675+
if (!adev->reset_domain)
3676+
return -ENOMEM;
3677+
36673678
/* detect hw virtualization here */
36683679
amdgpu_detect_virtualization(adev);
36693680

@@ -3673,15 +3684,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
36733684
return r;
36743685
}
36753686

3676-
/*
3677-
* Reset domain needs to be present early, before XGMI hive discovered
3678-
* (if any) and intitialized to use reset sem and in_gpu reset flag
3679-
* early on during init.
3680-
*/
3681-
adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE ,"amdgpu-reset-dev");
3682-
if (!adev->reset_domain)
3683-
return -ENOMEM;
3684-
36853687
/* early init functions */
36863688
r = amdgpu_device_ip_early_init(adev);
36873689
if (r)

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

Lines changed: 22 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -622,6 +622,13 @@ void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev)
622622
{
623623
unsigned size;
624624

625+
/*
626+
* Some ASICs need to reserve a region of video memory to avoid access
627+
* from driver
628+
*/
629+
adev->mman.stolen_reserved_offset = 0;
630+
adev->mman.stolen_reserved_size = 0;
631+
625632
/*
626633
* TODO:
627634
* Currently there is a bug where some memory client outside
@@ -632,10 +639,25 @@ void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev)
632639
*/
633640
switch (adev->asic_type) {
634641
case CHIP_VEGA10:
642+
adev->mman.keep_stolen_vga_memory = true;
643+
/*
644+
* VEGA10 SRIOV VF needs some firmware reserved area.
645+
*/
646+
if (amdgpu_sriov_vf(adev)) {
647+
adev->mman.stolen_reserved_offset = 0x100000;
648+
adev->mman.stolen_reserved_size = 0x600000;
649+
}
650+
break;
635651
case CHIP_RAVEN:
636652
case CHIP_RENOIR:
637653
adev->mman.keep_stolen_vga_memory = true;
638654
break;
655+
case CHIP_YELLOW_CARP:
656+
if (amdgpu_discovery == 0) {
657+
adev->mman.stolen_reserved_offset = 0x1ffb0000;
658+
adev->mman.stolen_reserved_size = 64 * PAGE_SIZE;
659+
}
660+
break;
639661
default:
640662
adev->mman.keep_stolen_vga_memory = false;
641663
break;
@@ -756,25 +778,6 @@ uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo
756778
return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base;
757779
}
758780

759-
void amdgpu_gmc_get_reserved_allocation(struct amdgpu_device *adev)
760-
{
761-
/* Some ASICs need to reserve a region of video memory to avoid access
762-
* from driver */
763-
adev->mman.stolen_reserved_offset = 0;
764-
adev->mman.stolen_reserved_size = 0;
765-
766-
switch (adev->asic_type) {
767-
case CHIP_YELLOW_CARP:
768-
if (amdgpu_discovery == 0) {
769-
adev->mman.stolen_reserved_offset = 0x1ffb0000;
770-
adev->mman.stolen_reserved_size = 64 * PAGE_SIZE;
771-
}
772-
break;
773-
default:
774-
break;
775-
}
776-
}
777-
778781
int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
779782
{
780783
struct amdgpu_bo *vram_bo = NULL;

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -331,7 +331,6 @@ amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
331331
bool enable);
332332

333333
void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev);
334-
void amdgpu_gmc_get_reserved_allocation(struct amdgpu_device *adev);
335334

336335
void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev);
337336
uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -166,8 +166,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
166166
}
167167

168168
if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) &&
169-
(ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)) {
170-
dev_err(adev->dev, "secure submissions not supported on compute rings\n");
169+
(!ring->funcs->secure_submission_supported)) {
170+
dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name);
171171
return -EINVAL;
172172
}
173173

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -310,6 +310,10 @@ static int psp_sw_init(void *handle)
310310
return ret;
311311
}
312312

313+
adev->psp.xgmi_context.supports_extended_data =
314+
!adev->gmc.xgmi.connected_to_cpu &&
315+
adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
316+
313317
memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
314318
if (psp_get_runtime_db_entry(adev,
315319
PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
@@ -3008,7 +3012,6 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev)
30083012
adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
30093013
adev->psp.sos.start_addr = ucode_array_start_addr +
30103014
le32_to_cpu(sos_hdr->sos.offset_bytes);
3011-
adev->psp.xgmi_context.supports_extended_data = false;
30123015
} else {
30133016
/* Load alternate PSP SOS FW */
30143017
sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
@@ -3023,7 +3026,6 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev)
30233026
adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
30243027
adev->psp.sos.start_addr = ucode_array_start_addr +
30253028
le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3026-
adev->psp.xgmi_context.supports_extended_data = true;
30273029
}
30283030

30293031
if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2068,6 +2068,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
20682068
mutex_init(&con->recovery_lock);
20692069
INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
20702070
atomic_set(&con->in_recovery, 0);
2071+
con->eeprom_control.bad_channel_bitmap = 0;
20712072

20722073
max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count();
20732074
amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
@@ -2092,6 +2093,11 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
20922093
goto free;
20932094

20942095
amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2096+
2097+
if (con->update_channel_flag == true) {
2098+
amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2099+
con->update_channel_flag = false;
2100+
}
20952101
}
20962102

20972103
#ifdef CONFIG_X86_MCE_AMD
@@ -2285,6 +2291,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
22852291
goto release_con;
22862292
}
22872293

2294+
con->update_channel_flag = false;
22882295
con->features = 0;
22892296
INIT_LIST_HEAD(&con->head);
22902297
/* Might need get this flag from vbios. */

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -374,6 +374,9 @@ struct amdgpu_ras {
374374

375375
/* record umc error info queried from smu */
376376
struct umc_ecc_info umc_ecc;
377+
378+
/* Indicates smu whether need update bad channel info */
379+
bool update_channel_flag;
377380
};
378381

379382
struct ras_fs_data {

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c

Lines changed: 23 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -267,6 +267,7 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
267267
{
268268
struct amdgpu_device *adev = to_amdgpu_device(control);
269269
struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
270+
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
270271
u8 csum;
271272
int res;
272273

@@ -287,6 +288,10 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
287288

288289
amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs);
289290

291+
control->bad_channel_bitmap = 0;
292+
amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap);
293+
con->update_channel_flag = false;
294+
290295
amdgpu_ras_debugfs_set_ret_size(control);
291296

292297
mutex_unlock(&control->ras_tbl_mutex);
@@ -420,6 +425,7 @@ amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,
420425
struct eeprom_table_record *record,
421426
const u32 num)
422427
{
428+
struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control));
423429
u32 a, b, i;
424430
u8 *buf, *pp;
425431
int res;
@@ -431,9 +437,16 @@ amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,
431437
/* Encode all of them in one go.
432438
*/
433439
pp = buf;
434-
for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE)
440+
for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) {
435441
__encode_table_record_to_buf(control, &record[i], pp);
436442

443+
/* update bad channel bitmap */
444+
if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
445+
control->bad_channel_bitmap |= 1 << record[i].mem_channel;
446+
con->update_channel_flag = true;
447+
}
448+
}
449+
437450
/* a, first record index to write into.
438451
* b, last record index to write into.
439452
* a = first index to read (fri) + number of records in the table,
@@ -686,6 +699,7 @@ int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
686699
const u32 num)
687700
{
688701
struct amdgpu_device *adev = to_amdgpu_device(control);
702+
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
689703
int i, res;
690704
u8 *buf, *pp;
691705
u32 g0, g1;
@@ -753,8 +767,15 @@ int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
753767
/* Read up everything? Then transform.
754768
*/
755769
pp = buf;
756-
for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE)
770+
for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) {
757771
__decode_table_record_from_buf(control, &record[i], pp);
772+
773+
/* update bad channel bitmap */
774+
if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
775+
control->bad_channel_bitmap |= 1 << record[i].mem_channel;
776+
con->update_channel_flag = true;
777+
}
778+
}
758779
Out:
759780
kfree(buf);
760781
mutex_unlock(&control->ras_tbl_mutex);

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,10 @@ struct amdgpu_ras_eeprom_control {
8080
/* Protect table access via this mutex.
8181
*/
8282
struct mutex ras_tbl_mutex;
83+
84+
/* Record channel info which occurred bad pages
85+
*/
86+
u32 bad_channel_bitmap;
8387
};
8488

8589
/*

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -155,6 +155,7 @@ struct amdgpu_ring_funcs {
155155
u32 nop;
156156
bool support_64bit_ptrs;
157157
bool no_user_fence;
158+
bool secure_submission_supported;
158159
unsigned vmhub;
159160
unsigned extra_dw;
160161

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,11 @@ static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev,
9797
amdgpu_ras_save_bad_pages(adev);
9898

9999
amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
100+
101+
if (con->update_channel_flag == true) {
102+
amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
103+
con->update_channel_flag = false;
104+
}
100105
}
101106

102107
if (reset)

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

Lines changed: 0 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,6 @@
3434

3535
#include "amdgpu_reset.h"
3636

37-
#define smnPCS_XGMI23_PCS_ERROR_STATUS 0x11a01210
3837
#define smnPCS_XGMI3X16_PCS_ERROR_STATUS 0x11a0020c
3938
#define smnPCS_GOPX1_PCS_ERROR_STATUS 0x12200210
4039

@@ -69,17 +68,6 @@ static const int wafl_pcs_err_status_reg_arct[] = {
6968
smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
7069
};
7170

72-
static const int xgmi23_pcs_err_status_reg_aldebaran[] = {
73-
smnPCS_XGMI23_PCS_ERROR_STATUS,
74-
smnPCS_XGMI23_PCS_ERROR_STATUS + 0x100000,
75-
smnPCS_XGMI23_PCS_ERROR_STATUS + 0x200000,
76-
smnPCS_XGMI23_PCS_ERROR_STATUS + 0x300000,
77-
smnPCS_XGMI23_PCS_ERROR_STATUS + 0x400000,
78-
smnPCS_XGMI23_PCS_ERROR_STATUS + 0x500000,
79-
smnPCS_XGMI23_PCS_ERROR_STATUS + 0x600000,
80-
smnPCS_XGMI23_PCS_ERROR_STATUS + 0x700000
81-
};
82-
8371
static const int xgmi3x16_pcs_err_status_reg_aldebaran[] = {
8472
smnPCS_XGMI3X16_PCS_ERROR_STATUS,
8573
smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000,
@@ -797,9 +785,6 @@ static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev)
797785
xgmi_pcs_err_status_reg_vg20[i]);
798786
break;
799787
case CHIP_ALDEBARAN:
800-
for (i = 0; i < ARRAY_SIZE(xgmi23_pcs_err_status_reg_aldebaran); i++)
801-
pcs_clear_status(adev,
802-
xgmi23_pcs_err_status_reg_aldebaran[i]);
803788
for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++)
804789
pcs_clear_status(adev,
805790
xgmi3x16_pcs_err_status_reg_aldebaran[i]);
@@ -900,13 +885,6 @@ static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
900885
}
901886
break;
902887
case CHIP_ALDEBARAN:
903-
/* check xgmi23 pcs error */
904-
for (i = 0; i < ARRAY_SIZE(xgmi23_pcs_err_status_reg_aldebaran); i++) {
905-
data = RREG32_PCIE(xgmi23_pcs_err_status_reg_aldebaran[i]);
906-
if (data)
907-
amdgpu_xgmi_query_pcs_error_status(adev,
908-
data, &ue_cnt, &ce_cnt, true);
909-
}
910888
/* check xgmi3x16 pcs error */
911889
for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) {
912890
data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]);

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