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[Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics
This patch adds support for the following SME ACLE intrinsics (as defined in https://arm-software.github.io/acle/main/acle.html): - svld1_hor_za8 // also for _za16, _za32, _za64 and _za128 - svld1_hor_vnum_za8 // also for _za16, _za32, _za64 and _za128 - svld1_ver_za8 // also for _za16, _za32, _za64 and _za128 - svld1_ver_vnum_za8 // also for _za16, _za32, _za64 and _za128 - svst1_hor_za8 // also for _za16, _za32, _za64 and _za128 - svst1_hor_vnum_za8 // also for _za16, _za32, _za64 and _za128 - svst1_ver_za8 // also for _za16, _za32, _za64 and _za128 - svst1_ver_vnum_za8 // also for _za16, _za32, _za64 and _za128 SveEmitter.cpp is extended to generate arm_sme.h (currently named arm_sme_draft_spec_subject_to_change.h) and other SME definitions from arm_sme.td, which is modeled after arm_sve.td. Common TableGen definitions are moved into arm_sve_sme_incl.td. Co-authored-by: Sagar Kulkarni <[email protected]> Reviewed By: sdesmalen, kmclaughlin Differential Revision: https://reviews.llvm.org/D127910
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‎clang/include/clang/Basic/BuiltinsAArch64.def

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@@ -269,4 +269,5 @@ TARGET_HEADER_BUILTIN(__readx18qword, "ULLiULi", "nh", INTRIN_H, ALL_MS_LANGUAGE
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#undef BUILTIN
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#undef LANGBUILTIN
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#undef TARGET_BUILTIN
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#undef TARGET_HEADER_BUILTIN

‎clang/include/clang/Basic/BuiltinsARM.def

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@@ -343,4 +343,5 @@ TARGET_HEADER_BUILTIN(_InterlockedDecrement64_rel, "LLiLLiD*", "nh", INTRIN_H, A
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#undef BUILTIN
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#undef LANGBUILTIN
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#undef TARGET_BUILTIN
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#undef TARGET_HEADER_BUILTIN

‎clang/include/clang/Basic/BuiltinsNEON.def

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#undef GET_NEON_BUILTINS
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#undef BUILTIN
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#undef TARGET_BUILTIN

‎clang/include/clang/Basic/BuiltinsSME.def

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//===--- BuiltinsSME.def - SME Builtin function database --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the SME-specific builtin function database. Users of
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// this file must define the BUILTIN macro to make use of this information.
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//
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//===----------------------------------------------------------------------===//
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// The format of this database matches clang/Basic/Builtins.def.
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#define GET_SME_BUILTINS
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#include "clang/Basic/arm_sme_builtins.inc"
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#undef GET_SME_BUILTINS
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#undef BUILTIN
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#undef TARGET_BUILTIN

‎clang/include/clang/Basic/CMakeLists.txt

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@@ -72,6 +72,15 @@ clang_tablegen(arm_sve_typeflags.inc -gen-arm-sve-typeflags
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clang_tablegen(arm_sve_sema_rangechecks.inc -gen-arm-sve-sema-rangechecks
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SOURCE arm_sve.td
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TARGET ClangARMSveSemaRangeChecks)
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clang_tablegen(arm_sme_builtins.inc -gen-arm-sme-builtins
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SOURCE arm_sme.td
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TARGET ClangARMSmeBuiltins)
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clang_tablegen(arm_sme_builtin_cg.inc -gen-arm-sme-builtin-codegen
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SOURCE arm_sme.td
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TARGET ClangARMSmeBuiltinCG)
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clang_tablegen(arm_sme_sema_rangechecks.inc -gen-arm-sme-sema-rangechecks
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SOURCE arm_sme.td
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TARGET ClangARMSmeSemaRangeChecks)
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clang_tablegen(arm_cde_builtins.inc -gen-arm-cde-builtin-def
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SOURCE arm_cde.td
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TARGET ClangARMCdeBuiltinsDef)

‎clang/include/clang/Basic/TargetBuiltins.h

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enum {
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LastNEONBuiltin = NEON::FirstTSBuiltin - 1,
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#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
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#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BI##ID,
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#include "clang/Basic/BuiltinsSVE.def"
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FirstTSBuiltin,
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};
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}
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namespace SME {
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enum {
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LastSVEBuiltin = SVE::FirstTSBuiltin - 1,
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#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
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#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BI##ID,
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#include "clang/Basic/BuiltinsSME.def"
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FirstTSBuiltin,
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};
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}
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/// AArch64 builtins
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namespace AArch64 {
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enum {
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LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1,
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LastNEONBuiltin = NEON::FirstTSBuiltin - 1,
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FirstSVEBuiltin = NEON::FirstTSBuiltin,
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LastSVEBuiltin = SVE::FirstTSBuiltin - 1,
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FirstSMEBuiltin = SVE::FirstTSBuiltin,
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LastSMEBuiltin = SME::FirstTSBuiltin - 1,
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#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
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#include "clang/Basic/BuiltinsAArch64.def"
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LastTSBuiltin

‎clang/include/clang/Basic/arm_sme.td

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//===--- arm_sme.td - ARM SME compiler interface ------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the TableGen definitions from which the ARM SME header
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// file will be generated. See:
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//
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// https://developer.arm.com/architectures/system-architectures/software-standards/acle
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//
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//===----------------------------------------------------------------------===//
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include "arm_sve_sme_incl.td"
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////////////////////////////////////////////////////////////////////////////////
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// Loads
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multiclass ZALoad<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> {
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let TargetGuard = "sme" in {
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def NAME # _H : MInst<"svld1_hor_" # n_suffix, "vimiPQ", t,
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[IsLoad, IsOverloadNone, IsStreaming, IsSharedZA],
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MemEltTyDefault, i_prefix # "_horiz", ch>;
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def NAME # _H_VNUM : MInst<"svld1_hor_vnum_" # n_suffix, "vimiPQl", t,
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[IsLoad, IsOverloadNone, IsStreaming, IsSharedZA],
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MemEltTyDefault, i_prefix # "_horiz", ch>;
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def NAME # _V : MInst<"svld1_ver_" # n_suffix, "vimiPQ", t,
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[IsLoad, IsOverloadNone, IsStreaming, IsSharedZA],
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MemEltTyDefault, i_prefix # "_vert", ch>;
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def NAME # _V_VNUM : MInst<"svld1_ver_vnum_" # n_suffix, "vimiPQl", t,
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[IsLoad, IsOverloadNone, IsStreaming, IsSharedZA],
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MemEltTyDefault, i_prefix # "_vert", ch>;
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}
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}
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defm SVLD1_ZA8 : ZALoad<"za8", "c", "aarch64_sme_ld1b", [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_15>]>;
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defm SVLD1_ZA16 : ZALoad<"za16", "s", "aarch64_sme_ld1h", [ImmCheck<0, ImmCheck0_1>, ImmCheck<2, ImmCheck0_7>]>;
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defm SVLD1_ZA32 : ZALoad<"za32", "i", "aarch64_sme_ld1w", [ImmCheck<0, ImmCheck0_3>, ImmCheck<2, ImmCheck0_3>]>;
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defm SVLD1_ZA64 : ZALoad<"za64", "l", "aarch64_sme_ld1d", [ImmCheck<0, ImmCheck0_7>, ImmCheck<2, ImmCheck0_1>]>;
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defm SVLD1_ZA128 : ZALoad<"za128", "q", "aarch64_sme_ld1q", [ImmCheck<0, ImmCheck0_15>, ImmCheck<2, ImmCheck0_0>]>;
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////////////////////////////////////////////////////////////////////////////////
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// Stores
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multiclass ZAStore<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> {
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let TargetGuard = "sme" in {
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def NAME # _H : MInst<"svst1_hor_" # n_suffix, "vimiP%", t,
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[IsStore, IsOverloadNone, IsStreaming, IsSharedZA, IsPreservesZA],
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MemEltTyDefault, i_prefix # "_horiz", ch>;
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def NAME # _H_VNUM : MInst<"svst1_hor_vnum_" # n_suffix, "vimiP%l", t,
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[IsStore, IsOverloadNone, IsStreaming, IsSharedZA, IsPreservesZA],
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MemEltTyDefault, i_prefix # "_horiz", ch>;
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def NAME # _V : MInst<"svst1_ver_" # n_suffix, "vimiP%", t,
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[IsStore, IsOverloadNone, IsStreaming, IsSharedZA, IsPreservesZA],
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MemEltTyDefault, i_prefix # "_vert", ch>;
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def NAME # _V_VNUM : MInst<"svst1_ver_vnum_" # n_suffix, "vimiP%l", t,
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[IsStore, IsOverloadNone, IsStreaming, IsSharedZA, IsPreservesZA],
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MemEltTyDefault, i_prefix # "_vert", ch>;
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}
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}
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defm SVST1_ZA8 : ZAStore<"za8", "c", "aarch64_sme_st1b", [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_15>]>;
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defm SVST1_ZA16 : ZAStore<"za16", "s", "aarch64_sme_st1h", [ImmCheck<0, ImmCheck0_1>, ImmCheck<2, ImmCheck0_7>]>;
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defm SVST1_ZA32 : ZAStore<"za32", "i", "aarch64_sme_st1w", [ImmCheck<0, ImmCheck0_3>, ImmCheck<2, ImmCheck0_3>]>;
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defm SVST1_ZA64 : ZAStore<"za64", "l", "aarch64_sme_st1d", [ImmCheck<0, ImmCheck0_7>, ImmCheck<2, ImmCheck0_1>]>;
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defm SVST1_ZA128 : ZAStore<"za128", "q", "aarch64_sme_st1q", [ImmCheck<0, ImmCheck0_15>, ImmCheck<2, ImmCheck0_0>]>;

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