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aneftinJeff Kirsher
aneftin
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Jeff Kirsher
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igc: Add interrupt support
This patch set adds interrupt support for the igc interfaces. Signed-off-by: Sasha Neftin <[email protected]> Tested-by: Aaron Brown <[email protected]> Signed-off-by: Jeff Kirsher <[email protected]>
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‎drivers/net/ethernet/intel/igc/igc.h

Lines changed: 127 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,17 @@
2828
extern char igc_driver_name[];
2929
extern char igc_driver_version[];
3030

31+
/* Interrupt defines */
32+
#define IGC_START_ITR 648 /* ~6000 ints/sec */
33+
#define IGC_FLAG_HAS_MSI BIT(0)
34+
#define IGC_FLAG_QUEUE_PAIRS BIT(4)
35+
#define IGC_FLAG_HAS_MSIX BIT(13)
36+
37+
#define IGC_START_ITR 648 /* ~6000 ints/sec */
38+
#define IGC_4K_ITR 980
39+
#define IGC_20K_ITR 196
40+
#define IGC_70K_ITR 56
41+
3142
/* Transmit and receive queues */
3243
#define IGC_MAX_RX_QUEUES 4
3344
#define IGC_MAX_TX_QUEUES 4
@@ -42,10 +53,96 @@ enum igc_state_t {
4253
__IGC_PTP_TX_IN_PROGRESS,
4354
};
4455

56+
struct igc_tx_queue_stats {
57+
u64 packets;
58+
u64 bytes;
59+
u64 restart_queue;
60+
};
61+
62+
struct igc_rx_queue_stats {
63+
u64 packets;
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u64 bytes;
65+
u64 drops;
66+
u64 csum_err;
67+
u64 alloc_failed;
68+
};
69+
70+
struct igc_rx_packet_stats {
71+
u64 ipv4_packets; /* IPv4 headers processed */
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u64 ipv4e_packets; /* IPv4E headers with extensions processed */
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u64 ipv6_packets; /* IPv6 headers processed */
74+
u64 ipv6e_packets; /* IPv6E headers with extensions processed */
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u64 tcp_packets; /* TCP headers processed */
76+
u64 udp_packets; /* UDP headers processed */
77+
u64 sctp_packets; /* SCTP headers processed */
78+
u64 nfs_packets; /* NFS headers processe */
79+
u64 other_packets;
80+
};
81+
82+
struct igc_ring_container {
83+
struct igc_ring *ring; /* pointer to linked list of rings */
84+
unsigned int total_bytes; /* total bytes processed this int */
85+
unsigned int total_packets; /* total packets processed this int */
86+
u16 work_limit; /* total work allowed per interrupt */
87+
u8 count; /* total number of rings in vector */
88+
u8 itr; /* current ITR setting for ring */
89+
};
90+
91+
struct igc_ring {
92+
struct igc_q_vector *q_vector; /* backlink to q_vector */
93+
struct net_device *netdev; /* back pointer to net_device */
94+
struct device *dev; /* device for dma mapping */
95+
union { /* array of buffer info structs */
96+
struct igc_tx_buffer *tx_buffer_info;
97+
struct igc_rx_buffer *rx_buffer_info;
98+
};
99+
void *desc; /* descriptor ring memory */
100+
unsigned long flags; /* ring specific flags */
101+
void __iomem *tail; /* pointer to ring tail register */
102+
dma_addr_t dma; /* phys address of the ring */
103+
unsigned int size; /* length of desc. ring in bytes */
104+
105+
u16 count; /* number of desc. in the ring */
106+
u8 queue_index; /* logical index of the ring*/
107+
u8 reg_idx; /* physical index of the ring */
108+
109+
/* everything past this point are written often */
110+
u16 next_to_clean;
111+
u16 next_to_use;
112+
u16 next_to_alloc;
113+
114+
union {
115+
/* TX */
116+
struct {
117+
struct igc_tx_queue_stats tx_stats;
118+
};
119+
/* RX */
120+
struct {
121+
struct igc_rx_queue_stats rx_stats;
122+
struct igc_rx_packet_stats pkt_stats;
123+
struct sk_buff *skb;
124+
};
125+
};
126+
} ____cacheline_internodealigned_in_smp;
127+
45128
struct igc_q_vector {
46129
struct igc_adapter *adapter; /* backlink */
130+
void __iomem *itr_register;
131+
u32 eims_value; /* EIMS mask value */
132+
133+
u16 itr_val;
134+
u8 set_itr;
135+
136+
struct igc_ring_container rx, tx;
47137

48138
struct napi_struct napi;
139+
140+
struct rcu_head rcu; /* to avoid race with update stats on free */
141+
char name[IFNAMSIZ + 9];
142+
struct net_device poll_dev;
143+
144+
/* for dynamic allocation of rings associated with this q_vector */
145+
struct igc_ring ring[0] ____cacheline_internodealigned_in_smp;
49146
};
50147

51148
struct igc_mac_addr {
@@ -65,13 +162,35 @@ struct igc_adapter {
65162
unsigned long state;
66163
unsigned int flags;
67164
unsigned int num_q_vectors;
165+
166+
struct msix_entry *msix_entries;
167+
168+
/* TX */
169+
u16 tx_work_limit;
170+
int num_tx_queues;
171+
struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
172+
173+
/* RX */
174+
int num_rx_queues;
175+
struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
176+
177+
struct timer_list watchdog_timer;
178+
struct timer_list dma_err_timer;
179+
struct timer_list phy_info_timer;
180+
68181
u16 link_speed;
69182
u16 link_duplex;
70183

71184
u8 port_num;
72185

73186
u8 __iomem *io_addr;
187+
/* Interrupt Throttle Rate */
188+
u32 rx_itr_setting;
189+
u32 tx_itr_setting;
190+
191+
struct work_struct reset_task;
74192
struct work_struct watchdog_task;
193+
struct work_struct dma_err_task;
75194

76195
int msg_enable;
77196
u32 max_frame_size;
@@ -81,8 +200,16 @@ struct igc_adapter {
81200

82201
/* structs defined in igc_hw.h */
83202
struct igc_hw hw;
203+
struct igc_hw_stats stats;
84204

85205
struct igc_q_vector *q_vector[MAX_Q_VECTORS];
206+
u32 eims_enable_mask;
207+
u32 eims_other;
208+
209+
u16 tx_ring_count;
210+
u16 rx_ring_count;
211+
212+
u32 rss_queues;
86213

87214
struct igc_mac_addr *mac_table;
88215
};

‎drivers/net/ethernet/intel/igc/igc_defines.h

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,4 +42,44 @@
4242
#define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
4343
#define IGC_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
4444

45+
/* Interrupt Cause Read */
46+
#define IGC_ICR_TXDW BIT(0) /* Transmit desc written back */
47+
#define IGC_ICR_TXQE BIT(1) /* Transmit Queue empty */
48+
#define IGC_ICR_LSC BIT(2) /* Link Status Change */
49+
#define IGC_ICR_RXSEQ BIT(3) /* Rx sequence error */
50+
#define IGC_ICR_RXDMT0 BIT(4) /* Rx desc min. threshold (0) */
51+
#define IGC_ICR_RXO BIT(6) /* Rx overrun */
52+
#define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */
53+
#define IGC_ICR_DRSTA BIT(30) /* Device Reset Asserted */
54+
#define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
55+
56+
#define IMS_ENABLE_MASK ( \
57+
IGC_IMS_RXT0 | \
58+
IGC_IMS_TXDW | \
59+
IGC_IMS_RXDMT0 | \
60+
IGC_IMS_RXSEQ | \
61+
IGC_IMS_LSC)
62+
63+
/* Interrupt Mask Set */
64+
#define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */
65+
#define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
66+
#define IGC_IMS_LSC IGC_ICR_LSC /* Link Status Change */
67+
#define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */
68+
#define IGC_IMS_DRSTA IGC_ICR_DRSTA /* Device Reset Asserted */
69+
#define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
70+
#define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
71+
72+
#define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
73+
#define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */
74+
75+
#define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
76+
#define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
77+
#define IGC_IVAR_VALID 0x80
78+
#define IGC_GPIE_NSICR 0x00000001
79+
#define IGC_GPIE_MSIX_MODE 0x00000010
80+
#define IGC_GPIE_EIAME 0x40000000
81+
#define IGC_GPIE_PBA 0x80000000
82+
83+
#define IGC_N0_QUEUE -1
84+
4585
#endif /* _IGC_DEFINES_H_ */

‎drivers/net/ethernet/intel/igc/igc_hw.h

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,90 @@ struct igc_hw {
8585
u8 revision_id;
8686
};
8787

88+
/* Statistics counters collected by the MAC */
89+
struct igc_hw_stats {
90+
u64 crcerrs;
91+
u64 algnerrc;
92+
u64 symerrs;
93+
u64 rxerrc;
94+
u64 mpc;
95+
u64 scc;
96+
u64 ecol;
97+
u64 mcc;
98+
u64 latecol;
99+
u64 colc;
100+
u64 dc;
101+
u64 tncrs;
102+
u64 sec;
103+
u64 cexterr;
104+
u64 rlec;
105+
u64 xonrxc;
106+
u64 xontxc;
107+
u64 xoffrxc;
108+
u64 xofftxc;
109+
u64 fcruc;
110+
u64 prc64;
111+
u64 prc127;
112+
u64 prc255;
113+
u64 prc511;
114+
u64 prc1023;
115+
u64 prc1522;
116+
u64 gprc;
117+
u64 bprc;
118+
u64 mprc;
119+
u64 gptc;
120+
u64 gorc;
121+
u64 gotc;
122+
u64 rnbc;
123+
u64 ruc;
124+
u64 rfc;
125+
u64 roc;
126+
u64 rjc;
127+
u64 mgprc;
128+
u64 mgpdc;
129+
u64 mgptc;
130+
u64 tor;
131+
u64 tot;
132+
u64 tpr;
133+
u64 tpt;
134+
u64 ptc64;
135+
u64 ptc127;
136+
u64 ptc255;
137+
u64 ptc511;
138+
u64 ptc1023;
139+
u64 ptc1522;
140+
u64 mptc;
141+
u64 bptc;
142+
u64 tsctc;
143+
u64 tsctfc;
144+
u64 iac;
145+
u64 icrxptc;
146+
u64 icrxatc;
147+
u64 ictxptc;
148+
u64 ictxatc;
149+
u64 ictxqec;
150+
u64 ictxqmtc;
151+
u64 icrxdmtc;
152+
u64 icrxoc;
153+
u64 cbtmpc;
154+
u64 htdpmc;
155+
u64 cbrdpc;
156+
u64 cbrmpc;
157+
u64 rpthc;
158+
u64 hgptc;
159+
u64 htcbdpc;
160+
u64 hgorc;
161+
u64 hgotc;
162+
u64 lenerrs;
163+
u64 scvpc;
164+
u64 hrmpc;
165+
u64 doosync;
166+
u64 o2bgptc;
167+
u64 o2bspc;
168+
u64 b2ospc;
169+
u64 b2ogprc;
170+
};
171+
88172
s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
89173
s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
90174
void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);

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