@@ -68,15 +68,6 @@ tablegen("RISCVGenPostLegalizeGICombiner") {
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td_file = " RISCVGISel.td"
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}
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- tablegen (" RISCVGenPostLegalizeGILowering" ) {
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- visibility = [ " :LLVMRISCVCodeGen" ]
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- args = [
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- " -gen-global-isel-combiner" ,
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- " -combiners=RISCVPostLegalizerLowering" ,
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- ]
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- td_file = " RISCVGISel.td"
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- }
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-
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tablegen (" RISCVGenRegisterBank" ) {
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visibility = [ " :LLVMRISCVCodeGen" ]
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args = [ " -gen-register-bank" ]
@@ -92,7 +83,6 @@ static_library("LLVMRISCVCodeGen") {
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" :RISCVGenMacroFusion" ,
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" :RISCVGenO0PreLegalizeGICombiner" ,
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" :RISCVGenPostLegalizeGICombiner" ,
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- " :RISCVGenPostLegalizeGILowering" ,
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" :RISCVGenPreLegalizeGICombiner" ,
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" :RISCVGenRegisterBank" ,
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@@ -119,7 +109,6 @@ static_library("LLVMRISCVCodeGen") {
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" GISel/RISCVLegalizerInfo.cpp" ,
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" GISel/RISCVO0PreLegalizerCombiner.cpp" ,
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" GISel/RISCVPostLegalizerCombiner.cpp" ,
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- " GISel/RISCVPostLegalizerLowering.cpp" ,
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" GISel/RISCVPreLegalizerCombiner.cpp" ,
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" GISel/RISCVRegisterBankInfo.cpp" ,
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" RISCVAsmPrinter.cpp" ,
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