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[RISCV][NFC] rvv refactoring
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2 files changed

+138
-143
lines changed

2 files changed

+138
-143
lines changed

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 138 additions & 138 deletions
Original file line numberDiff line numberDiff line change
@@ -27,64 +27,6 @@
2727

2828
using namespace llvm;
2929

30-
namespace {
31-
32-
class CFISaveRegisterEmitter {
33-
MachineFunction &m_MF;
34-
MachineFrameInfo &m_MFI;
35-
36-
public:
37-
CFISaveRegisterEmitter(MachineFunction &MF)
38-
: m_MF{MF}, m_MFI{MF.getFrameInfo()} {};
39-
40-
void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
41-
const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
42-
const DebugLoc &DL, const CalleeSavedInfo &CS) const {
43-
int FrameIdx = CS.getFrameIdx();
44-
int64_t Offset = m_MFI.getObjectOffset(FrameIdx);
45-
Register Reg = CS.getReg();
46-
unsigned CFIIndex = m_MF.addFrameInst(MCCFIInstruction::createOffset(
47-
nullptr, RI.getDwarfRegNum(Reg, true), Offset));
48-
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
49-
.addCFIIndex(CFIIndex)
50-
.setMIFlag(MachineInstr::FrameSetup);
51-
}
52-
};
53-
54-
class CFIRestoreRegisterEmitter {
55-
MachineFunction &m_MF;
56-
57-
public:
58-
CFIRestoreRegisterEmitter(MachineFunction &MF) : m_MF{MF} {};
59-
60-
void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
61-
const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
62-
const DebugLoc &DL, const CalleeSavedInfo &CS) const {
63-
Register Reg = CS.getReg();
64-
unsigned CFIIndex = m_MF.addFrameInst(
65-
MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true)));
66-
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
67-
.addCFIIndex(CFIIndex)
68-
.setMIFlag(MachineInstr::FrameDestroy);
69-
}
70-
};
71-
72-
} // namespace
73-
74-
template <typename Emitter>
75-
void RISCVFrameLowering::emitCFIForCSI(
76-
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
77-
const SmallVector<CalleeSavedInfo, 8> &CSI) const {
78-
MachineFunction *MF = MBB.getParent();
79-
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
80-
const RISCVInstrInfo *TII = STI.getInstrInfo();
81-
DebugLoc DL = MBB.findDebugLoc(MBBI);
82-
83-
Emitter E{*MF};
84-
for (const auto &CS : CSI)
85-
E.emit(MBB, MBBI, *RI, *TII, DL, CS);
86-
}
87-
8830
static Align getABIStackAlignment(RISCVABI::ABI ABI) {
8931
if (ABI == RISCVABI::ABI_ILP32E)
9032
return Align(4);
@@ -602,6 +544,142 @@ static MCCFIInstruction createDefCFAOffset(const TargetRegisterInfo &TRI,
602544
Comment.str());
603545
}
604546

547+
static unsigned getCalleeSavedRVVNumRegs(const Register &BaseReg) {
548+
return RISCV::VRRegClass.contains(BaseReg) ? 1
549+
: RISCV::VRM2RegClass.contains(BaseReg) ? 2
550+
: RISCV::VRM4RegClass.contains(BaseReg) ? 4
551+
: 8;
552+
}
553+
554+
static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
555+
const Register &Reg) {
556+
MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
557+
// If it's not a grouped vector register, it doesn't have subregister, so
558+
// the base register is just itself.
559+
if (BaseReg == RISCV::NoRegister)
560+
BaseReg = Reg;
561+
return BaseReg;
562+
}
563+
564+
namespace {
565+
566+
class CFISaveRegisterEmitter {
567+
MachineFunction &m_MF;
568+
MachineFrameInfo &m_MFI;
569+
570+
public:
571+
CFISaveRegisterEmitter(const RISCVFrameLowering &, MachineFunction &MF)
572+
: m_MF{MF}, m_MFI{MF.getFrameInfo()} {};
573+
574+
void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
575+
const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
576+
const DebugLoc &DL, const CalleeSavedInfo &CS) const {
577+
int FrameIdx = CS.getFrameIdx();
578+
int64_t Offset = m_MFI.getObjectOffset(FrameIdx);
579+
Register Reg = CS.getReg();
580+
unsigned CFIIndex = m_MF.addFrameInst(MCCFIInstruction::createOffset(
581+
nullptr, RI.getDwarfRegNum(Reg, true), Offset));
582+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
583+
.addCFIIndex(CFIIndex)
584+
.setMIFlag(MachineInstr::FrameSetup);
585+
}
586+
};
587+
588+
class CFIRestoreRegisterEmitter {
589+
MachineFunction &m_MF;
590+
591+
public:
592+
CFIRestoreRegisterEmitter(const RISCVFrameLowering &, MachineFunction &MF) : m_MF{MF} {};
593+
594+
void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
595+
const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
596+
const DebugLoc &DL, const CalleeSavedInfo &CS) const {
597+
Register Reg = CS.getReg();
598+
unsigned CFIIndex = m_MF.addFrameInst(
599+
MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true)));
600+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
601+
.addCFIIndex(CFIIndex)
602+
.setMIFlag(MachineInstr::FrameDestroy);
603+
}
604+
};
605+
606+
class CFISaveRVVRegisterEmitter {
607+
MachineFunction &m_MF;
608+
MachineFrameInfo &m_MFI;
609+
const uint64_t m_FixedSize;
610+
611+
static uint64_t getFixedSize(const RISCVFrameLowering &FL, MachineFunction &MF, MachineFrameInfo &MFI) {
612+
const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
613+
614+
uint64_t FixedSize = FL.getStackSizeWithRVVPadding(MF);
615+
if (!FL.hasFP(MF)) {
616+
uint64_t ScalarLocalVarSize =
617+
MFI.getStackSize() - RVFI->getCalleeSavedStackSize() -
618+
RVFI->getRVPushStackSize() - RVFI->getVarArgsSaveSize() +
619+
RVFI->getRVVPadding();
620+
FixedSize -= ScalarLocalVarSize;
621+
}
622+
return FixedSize;
623+
}
624+
625+
public:
626+
CFISaveRVVRegisterEmitter(const RISCVFrameLowering &FL, MachineFunction &MF) : m_MF{MF}, m_MFI{MF.getFrameInfo()}, m_FixedSize{getFixedSize(FL, MF, m_MFI)} {};
627+
628+
void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
629+
const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
630+
const DebugLoc &DL, const CalleeSavedInfo &CS) const {
631+
632+
// Insert the spill to the stack frame.
633+
int FI = CS.getFrameIdx();
634+
MCRegister BaseReg = getRVVBaseRegister(RI, CS.getReg());
635+
unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
636+
for (unsigned i = 0; i < NumRegs; ++i) {
637+
unsigned CFIIndex = m_MF.addFrameInst(createDefCFAOffset(
638+
RI, BaseReg + i, -m_FixedSize, m_MFI.getObjectOffset(FI) / 8 + i));
639+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
640+
.addCFIIndex(CFIIndex)
641+
.setMIFlag(MachineInstr::FrameSetup);
642+
}
643+
}
644+
};
645+
646+
class CFIRestoreRVVRegisterEmitter {
647+
MachineFunction &m_MF;
648+
649+
public:
650+
CFIRestoreRVVRegisterEmitter(const RISCVFrameLowering &, MachineFunction &MF) : m_MF{MF} {};
651+
652+
void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
653+
const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
654+
const DebugLoc &DL, const CalleeSavedInfo &CS) const {
655+
MCRegister BaseReg = getRVVBaseRegister(RI, CS.getReg());
656+
unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
657+
for (unsigned i = 0; i < NumRegs; ++i) {
658+
unsigned CFIIndex = m_MF.addFrameInst(MCCFIInstruction::createRestore(
659+
nullptr, RI.getDwarfRegNum(BaseReg + i, true)));
660+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
661+
.addCFIIndex(CFIIndex)
662+
.setMIFlag(MachineInstr::FrameDestroy);
663+
}
664+
}
665+
};
666+
667+
} // namespace
668+
669+
template <typename Emitter>
670+
void RISCVFrameLowering::emitCFIForCSI(
671+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
672+
const SmallVector<CalleeSavedInfo, 8> &CSI) const {
673+
MachineFunction *MF = MBB.getParent();
674+
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
675+
const RISCVInstrInfo *TII = STI.getInstrInfo();
676+
DebugLoc DL = MBB.findDebugLoc(MBBI);
677+
678+
Emitter E{*this, *MF};
679+
for (const auto &CS : CSI)
680+
E.emit(MBB, MBBI, *RI, *TII, DL, CS);
681+
}
682+
605683
void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
606684
MachineBasicBlock &MBB) const {
607685
MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -796,7 +874,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
796874
}
797875

798876
std::advance(MBBI, getRVVCalleeSavedInfo(MF, CSI).size());
799-
emitCalleeSavedRVVPrologCFI(MBB, MBBI, hasFP(MF));
877+
emitCFIForCSI<CFISaveRVVRegisterEmitter>(MBB, MBBI, getRVVCalleeSavedInfo(MF, CSI));
800878
}
801879

802880
if (hasFP(MF)) {
@@ -923,8 +1001,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
9231001
.addCFIIndex(CFIIndex)
9241002
.setMIFlag(MachineInstr::FrameDestroy);
9251003
}
926-
927-
emitCalleeSavedRVVEpilogCFI(MBB, LastFrameDestroy);
1004+
emitCFIForCSI<CFIRestoreRVVRegisterEmitter>(MBB, LastFrameDestroy, getRVVCalleeSavedInfo(MF, CSI));
9281005
}
9291006

9301007
if (FirstSPAdjustAmount) {
@@ -1712,83 +1789,6 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
17121789
return true;
17131790
}
17141791

1715-
static unsigned getCalleeSavedRVVNumRegs(const Register &BaseReg) {
1716-
return RISCV::VRRegClass.contains(BaseReg) ? 1
1717-
: RISCV::VRM2RegClass.contains(BaseReg) ? 2
1718-
: RISCV::VRM4RegClass.contains(BaseReg) ? 4
1719-
: 8;
1720-
}
1721-
1722-
static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
1723-
const Register &Reg) {
1724-
MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
1725-
// If it's not a grouped vector register, it doesn't have subregister, so
1726-
// the base register is just itself.
1727-
if (BaseReg == RISCV::NoRegister)
1728-
BaseReg = Reg;
1729-
return BaseReg;
1730-
}
1731-
1732-
void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
1733-
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, bool HasFP) const {
1734-
MachineFunction *MF = MBB.getParent();
1735-
const MachineFrameInfo &MFI = MF->getFrameInfo();
1736-
RISCVMachineFunctionInfo *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
1737-
const TargetInstrInfo &TII = *STI.getInstrInfo();
1738-
const RISCVRegisterInfo &TRI = *STI.getRegisterInfo();
1739-
DebugLoc DL = MBB.findDebugLoc(MI);
1740-
1741-
const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo());
1742-
if (RVVCSI.empty())
1743-
return;
1744-
1745-
uint64_t FixedSize = getStackSizeWithRVVPadding(*MF);
1746-
if (!HasFP) {
1747-
uint64_t ScalarLocalVarSize =
1748-
MFI.getStackSize() - RVFI->getCalleeSavedStackSize() -
1749-
RVFI->getRVPushStackSize() - RVFI->getVarArgsSaveSize() +
1750-
RVFI->getRVVPadding();
1751-
FixedSize -= ScalarLocalVarSize;
1752-
}
1753-
1754-
for (auto &CS : RVVCSI) {
1755-
// Insert the spill to the stack frame.
1756-
int FI = CS.getFrameIdx();
1757-
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
1758-
unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
1759-
for (unsigned i = 0; i < NumRegs; ++i) {
1760-
unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
1761-
TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i));
1762-
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1763-
.addCFIIndex(CFIIndex)
1764-
.setMIFlag(MachineInstr::FrameSetup);
1765-
}
1766-
}
1767-
}
1768-
1769-
void RISCVFrameLowering::emitCalleeSavedRVVEpilogCFI(
1770-
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
1771-
MachineFunction *MF = MBB.getParent();
1772-
const MachineFrameInfo &MFI = MF->getFrameInfo();
1773-
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
1774-
const TargetInstrInfo &TII = *STI.getInstrInfo();
1775-
const RISCVRegisterInfo &TRI = *STI.getRegisterInfo();
1776-
DebugLoc DL = MBB.findDebugLoc(MI);
1777-
1778-
const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo());
1779-
for (auto &CS : RVVCSI) {
1780-
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
1781-
unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
1782-
for (unsigned i = 0; i < NumRegs; ++i) {
1783-
unsigned CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore(
1784-
nullptr, RI->getDwarfRegNum(BaseReg + i, true)));
1785-
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1786-
.addCFIIndex(CFIIndex)
1787-
.setMIFlag(MachineInstr::FrameDestroy);
1788-
}
1789-
}
1790-
}
1791-
17921792
bool RISCVFrameLowering::restoreCalleeSavedRegisters(
17931793
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
17941794
MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

‎llvm/lib/Target/RISCV/RISCVFrameLowering.h

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -88,11 +88,6 @@ class RISCVFrameLowering : public TargetFrameLowering {
8888
void adjustStackForRVV(MachineFunction &MF, MachineBasicBlock &MBB,
8989
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
9090
int64_t Amount, MachineInstr::MIFlag Flag) const;
91-
void emitCalleeSavedRVVPrologCFI(MachineBasicBlock &MBB,
92-
MachineBasicBlock::iterator MI,
93-
bool HasFP) const;
94-
void emitCalleeSavedRVVEpilogCFI(MachineBasicBlock &MBB,
95-
MachineBasicBlock::iterator MI) const;
9691
template <typename Emitter>
9792
void emitCFIForCSI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
9893
const SmallVector<CalleeSavedInfo, 8> &CSI) const;

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