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[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
The VLMUL and policy enums originally lived in RISCVBaseInfo.h in the backend which is where everything else in the RISCVII namespace is defined. RISCVTargetParser.h is used by much more of the compiler and it doesn't really make sense to have 2 different namespaces exposed. These enums are both associated with VTYPE so using the RISCVVType namespace seems like a good home for them.
1 parent 0e1ffa3 commit 0cc532b

19 files changed

+207
-206
lines changed

‎llvm/include/llvm/TargetParser/RISCVTargetParser.h

Lines changed: 10 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ CPUModel getCPUModel(StringRef CPU);
6565

6666
} // namespace RISCV
6767

68-
namespace RISCVII {
68+
namespace RISCVVType {
6969
enum VLMUL : uint8_t {
7070
LMUL_1 = 0,
7171
LMUL_2,
@@ -82,9 +82,7 @@ enum {
8282
TAIL_AGNOSTIC = 1,
8383
MASK_AGNOSTIC = 2,
8484
};
85-
} // namespace RISCVII
8685

87-
namespace RISCVVType {
8886
// Is this a SEW value that can be encoded into the VTYPE format.
8987
inline static bool isValidSEW(unsigned SEW) {
9088
return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 64;
@@ -95,21 +93,21 @@ inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
9593
return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
9694
}
9795

98-
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
96+
unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
9997
bool MaskAgnostic);
10098

101-
inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
102-
unsigned VLMUL = VType & 0x7;
103-
return static_cast<RISCVII::VLMUL>(VLMUL);
99+
inline static VLMUL getVLMUL(unsigned VType) {
100+
unsigned VLMul = VType & 0x7;
101+
return static_cast<VLMUL>(VLMul);
104102
}
105103

106104
// Decode VLMUL into 1,2,4,8 and fractional indicator.
107-
std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
105+
std::pair<unsigned, bool> decodeVLMUL(VLMUL VLMul);
108106

109-
inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
107+
inline static VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
110108
assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
111109
unsigned LmulLog2 = Log2_32(LMUL);
112-
return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
110+
return static_cast<VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
113111
}
114112

115113
inline static unsigned decodeVSEW(unsigned VSEW) {
@@ -133,10 +131,9 @@ inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
133131

134132
void printVType(unsigned VType, raw_ostream &OS);
135133

136-
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
134+
unsigned getSEWLMULRatio(unsigned SEW, VLMUL VLMul);
137135

138-
std::optional<RISCVII::VLMUL>
139-
getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
136+
std::optional<VLMUL> getSameRatioLMUL(unsigned SEW, VLMUL VLMUL, unsigned EEW);
140137
} // namespace RISCVVType
141138

142139
} // namespace llvm

‎llvm/lib/Analysis/ValueTracking.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1984,7 +1984,7 @@ static void computeKnownBitsFromOperator(const Operator *I,
19841984
const ConstantRange Range = getVScaleRange(II->getFunction(), BitWidth);
19851985
uint64_t SEW = RISCVVType::decodeVSEW(
19861986
cast<ConstantInt>(II->getArgOperand(HasAVL))->getZExtValue());
1987-
RISCVII::VLMUL VLMUL = static_cast<RISCVII::VLMUL>(
1987+
RISCVVType::VLMUL VLMUL = static_cast<RISCVVType::VLMUL>(
19881988
cast<ConstantInt>(II->getArgOperand(1 + HasAVL))->getZExtValue());
19891989
uint64_t MaxVLEN =
19901990
Range.getUnsignedMax().getZExtValue() * RISCV::RVVBitsPerBlock;

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2311,7 +2311,7 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
23112311
}
23122312

23132313
if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
2314-
RISCVII::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional);
2314+
RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional);
23152315
if (Fractional) {
23162316
unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 : 32;
23172317
unsigned MaxSEW = ELEN / Lmul;

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1120,7 +1120,7 @@ bool RISCVLegalizerInfo::legalizeExtractSubvector(MachineInstr &MI,
11201120
// divide exactly.
11211121
assert(
11221122
RISCVVType::decodeVLMUL(RISCVTargetLowering::getLMUL(LitTyMVT)).second ||
1123-
RISCVTargetLowering::getLMUL(LitTyMVT) == RISCVII::VLMUL::LMUL_1);
1123+
RISCVTargetLowering::getLMUL(LitTyMVT) == RISCVVType::LMUL_1);
11241124

11251125
// If the vector type is an LMUL-group type, extract a subvector equal to the
11261126
// nearest full vector register type.
@@ -1143,7 +1143,7 @@ bool RISCVLegalizerInfo::legalizeExtractSubvector(MachineInstr &MI,
11431143
const LLT XLenTy(STI.getXLenVT());
11441144
auto SlidedownAmt = MIB.buildVScale(XLenTy, RemIdx);
11451145
auto [Mask, VL] = buildDefaultVLOps(LitTy, MIB, MRI);
1146-
uint64_t Policy = RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC;
1146+
uint64_t Policy = RISCVVType::TAIL_AGNOSTIC | RISCVVType::MASK_AGNOSTIC;
11471147
auto Slidedown = MIB.buildInstr(
11481148
RISCV::G_VSLIDEDOWN_VL, {InterLitTy},
11491149
{MIB.buildUndef(InterLitTy), Vec, SlidedownAmt, Mask, VL, Policy});
@@ -1265,10 +1265,10 @@ bool RISCVLegalizerInfo::legalizeInsertSubvector(MachineInstr &MI,
12651265
// Use tail agnostic policy if we're inserting over InterLitTy's tail.
12661266
ElementCount EndIndex =
12671267
ElementCount::getScalable(RemIdx) + LitTy.getElementCount();
1268-
uint64_t Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED;
1268+
uint64_t Policy = RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED;
12691269
if (STI.expandVScale(EndIndex) ==
12701270
STI.expandVScale(InterLitTy.getElementCount()))
1271-
Policy = RISCVII::TAIL_AGNOSTIC;
1271+
Policy = RISCVVType::TAIL_AGNOSTIC;
12721272

12731273
Inserted =
12741274
MIB.buildInstr(RISCV::G_VSLIDEUP_VL, {InsertedDst},

‎llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -107,32 +107,32 @@ RISCVInstrumentManager::createInstruments(const MCInst &Inst) {
107107
LLVM_DEBUG(dbgs() << "RVCB: Found VSETVLI and creating instrument for it: "
108108
<< Inst << "\n");
109109
unsigned VTypeI = Inst.getOperand(2).getImm();
110-
RISCVII::VLMUL VLMUL = RISCVVType::getVLMUL(VTypeI);
110+
RISCVVType::VLMUL VLMUL = RISCVVType::getVLMUL(VTypeI);
111111

112112
StringRef LMUL;
113113
switch (VLMUL) {
114-
case RISCVII::LMUL_1:
114+
case RISCVVType::LMUL_1:
115115
LMUL = "M1";
116116
break;
117-
case RISCVII::LMUL_2:
117+
case RISCVVType::LMUL_2:
118118
LMUL = "M2";
119119
break;
120-
case RISCVII::LMUL_4:
120+
case RISCVVType::LMUL_4:
121121
LMUL = "M4";
122122
break;
123-
case RISCVII::LMUL_8:
123+
case RISCVVType::LMUL_8:
124124
LMUL = "M8";
125125
break;
126-
case RISCVII::LMUL_F2:
126+
case RISCVVType::LMUL_F2:
127127
LMUL = "MF2";
128128
break;
129-
case RISCVII::LMUL_F4:
129+
case RISCVVType::LMUL_F4:
130130
LMUL = "MF4";
131131
break;
132-
case RISCVII::LMUL_F8:
132+
case RISCVVType::LMUL_F8:
133133
LMUL = "MF8";
134134
break;
135-
case RISCVII::LMUL_RESERVED:
135+
case RISCVVType::LMUL_RESERVED:
136136
llvm_unreachable("Cannot create instrument for LMUL_RESERVED");
137137
}
138138
SmallVector<UniqueInstrument> Instruments;
@@ -166,7 +166,7 @@ RISCVInstrumentManager::createInstruments(const MCInst &Inst) {
166166
}
167167

168168
static std::pair<uint8_t, uint8_t>
169-
getEEWAndEMUL(unsigned Opcode, RISCVII::VLMUL LMUL, uint8_t SEW) {
169+
getEEWAndEMUL(unsigned Opcode, RISCVVType::VLMUL LMUL, uint8_t SEW) {
170170
uint8_t EEW;
171171
switch (Opcode) {
172172
case RISCV::VLM_V:
@@ -249,7 +249,7 @@ unsigned RISCVInstrumentManager::getSchedClassID(
249249

250250
const RISCVVInversePseudosTable::PseudoInfo *RVV = nullptr;
251251
if (opcodeHasEEWAndEMULInfo(Opcode)) {
252-
RISCVII::VLMUL VLMUL = static_cast<RISCVII::VLMUL>(LMUL);
252+
RISCVVType::VLMUL VLMUL = static_cast<RISCVVType::VLMUL>(LMUL);
253253
auto [EEW, EMUL] = getEEWAndEMUL(Opcode, VLMUL, SEW);
254254
RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, EMUL, EEW);
255255
} else {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -141,8 +141,8 @@ static inline unsigned getFormat(uint64_t TSFlags) {
141141
return (TSFlags & InstFormatMask) >> InstFormatShift;
142142
}
143143
/// \returns the LMUL for the instruction.
144-
static inline VLMUL getLMul(uint64_t TSFlags) {
145-
return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
144+
static inline RISCVVType::VLMUL getLMul(uint64_t TSFlags) {
145+
return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
146146
}
147147
/// \returns true if this a _TIED pseudo.
148148
static inline bool isTiedPseudo(uint64_t TSFlags) {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -210,7 +210,7 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
210210
unsigned Imm = MI->getOperand(OpNo).getImm();
211211
// Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx,
212212
// or non-zero in bits 8 and above.
213-
if (RISCVVType::getVLMUL(Imm) == RISCVII::VLMUL::LMUL_RESERVED ||
213+
if (RISCVVType::getVLMUL(Imm) == RISCVVType::VLMUL::LMUL_RESERVED ||
214214
RISCVVType::getSEW(Imm) > 64 || (Imm >> 8) != 0) {
215215
O << formatImm(Imm);
216216
return;

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