[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC #127585
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…orceTailAgnostic. NFC Add a policy operand to set the tail agnostic policy instead of using ForceTailAgnostic. The masked to unmasked transforms had to be updated to drop the policy operand when converting to unmasked.
…n RISCVTargetParser.h. NFC The VLMUL and policy enums originally lived in RISCVBaseInfo.h in the backend which is where everything else in the RISCVII namespace is defined. RISCVTargetParser.h is used by much more of the compiler and it doesn't really make sense to have 2 different namespaces exposed.
llvmbot
added
backend:RISC-V
llvm:analysis
|
@llvm/pr-subscribers-backend-risc-v @llvm/pr-subscribers-llvm-analysis Author: Craig Topper (topperc) ChangesThe VLMUL and policy enums originally lived in RISCVBaseInfo.h in the RISCVTargetParser.h is used by much more of the compiler and it Patch is 78.86 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/127585.diff 23 Files Affected:
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index c237e1ddd6b38..b13a94cd56f2e 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -65,7 +65,7 @@ CPUModel getCPUModel(StringRef CPU);
} // namespace RISCV
-namespace RISCVII {
+namespace RISCVVType {
enum VLMUL : uint8_t {
LMUL_1 = 0,
LMUL_2,
@@ -82,9 +82,7 @@ enum {
TAIL_AGNOSTIC = 1,
MASK_AGNOSTIC = 2,
};
-} // namespace RISCVII
-namespace RISCVVType {
// Is this a SEW value that can be encoded into the VTYPE format.
inline static bool isValidSEW(unsigned SEW) {
return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 64;
@@ -95,21 +93,21 @@ inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
}
-unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
+unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
bool MaskAgnostic);
-inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
- unsigned VLMUL = VType & 0x7;
- return static_cast<RISCVII::VLMUL>(VLMUL);
+inline static VLMUL getVLMUL(unsigned VType) {
+ unsigned VLMul = VType & 0x7;
+ return static_cast<VLMUL>(VLMul);
}
// Decode VLMUL into 1,2,4,8 and fractional indicator.
-std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
+std::pair<unsigned, bool> decodeVLMUL(VLMUL VLMul);
-inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
+inline static VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
unsigned LmulLog2 = Log2_32(LMUL);
- return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
+ return static_cast<VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
}
inline static unsigned decodeVSEW(unsigned VSEW) {
@@ -133,10 +131,9 @@ inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
void printVType(unsigned VType, raw_ostream &OS);
-unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
+unsigned getSEWLMULRatio(unsigned SEW, VLMUL VLMul);
-std::optional<RISCVII::VLMUL>
-getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
+std::optional<VLMUL> getSameRatioLMUL(unsigned SEW, VLMUL VLMUL, unsigned EEW);
} // namespace RISCVVType
} // namespace llvm
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index 91a5f194db9dc..e3e026f7979da 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -1984,7 +1984,7 @@ static void computeKnownBitsFromOperator(const Operator *I,
const ConstantRange Range = getVScaleRange(II->getFunction(), BitWidth);
uint64_t SEW = RISCVVType::decodeVSEW(
cast<ConstantInt>(II->getArgOperand(HasAVL))->getZExtValue());
- RISCVII::VLMUL VLMUL = static_cast<RISCVII::VLMUL>(
+ RISCVVType::VLMUL VLMUL = static_cast<RISCVVType::VLMUL>(
cast<ConstantInt>(II->getArgOperand(1 + HasAVL))->getZExtValue());
uint64_t MaxVLEN =
Range.getUnsignedMax().getZExtValue() * RISCV::RVVBitsPerBlock;
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index ac87d72b7595c..6d4466b7abf53 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2311,7 +2311,7 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
}
if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
- RISCVII::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional);
+ RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional);
if (Fractional) {
unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 : 32;
unsigned MaxSEW = ELEN / Lmul;
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 6f0645965d737..56b1639143d8b 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -1120,7 +1120,7 @@ bool RISCVLegalizerInfo::legalizeExtractSubvector(MachineInstr &MI,
// divide exactly.
assert(
RISCVVType::decodeVLMUL(RISCVTargetLowering::getLMUL(LitTyMVT)).second ||
- RISCVTargetLowering::getLMUL(LitTyMVT) == RISCVII::VLMUL::LMUL_1);
+ RISCVTargetLowering::getLMUL(LitTyMVT) == RISCVVType::LMUL_1);
// If the vector type is an LMUL-group type, extract a subvector equal to the
// nearest full vector register type.
@@ -1143,7 +1143,7 @@ bool RISCVLegalizerInfo::legalizeExtractSubvector(MachineInstr &MI,
const LLT XLenTy(STI.getXLenVT());
auto SlidedownAmt = MIB.buildVScale(XLenTy, RemIdx);
auto [Mask, VL] = buildDefaultVLOps(LitTy, MIB, MRI);
- uint64_t Policy = RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC;
+ uint64_t Policy = RISCVVType::TAIL_AGNOSTIC | RISCVVType::MASK_AGNOSTIC;
auto Slidedown = MIB.buildInstr(
RISCV::G_VSLIDEDOWN_VL, {InterLitTy},
{MIB.buildUndef(InterLitTy), Vec, SlidedownAmt, Mask, VL, Policy});
@@ -1265,10 +1265,10 @@ bool RISCVLegalizerInfo::legalizeInsertSubvector(MachineInstr &MI,
// Use tail agnostic policy if we're inserting over InterLitTy's tail.
ElementCount EndIndex =
ElementCount::getScalable(RemIdx) + LitTy.getElementCount();
- uint64_t Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED;
+ uint64_t Policy = RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED;
if (STI.expandVScale(EndIndex) ==
STI.expandVScale(InterLitTy.getElementCount()))
- Policy = RISCVII::TAIL_AGNOSTIC;
+ Policy = RISCVVType::TAIL_AGNOSTIC;
Inserted =
MIB.buildInstr(RISCV::G_VSLIDEUP_VL, {InsertedDst},
diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
index fb0dc482e6081..0881de90700ab 100644
--- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
+++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
@@ -107,32 +107,32 @@ RISCVInstrumentManager::createInstruments(const MCInst &Inst) {
LLVM_DEBUG(dbgs() << "RVCB: Found VSETVLI and creating instrument for it: "
<< Inst << "\n");
unsigned VTypeI = Inst.getOperand(2).getImm();
- RISCVII::VLMUL VLMUL = RISCVVType::getVLMUL(VTypeI);
+ RISCVVType::VLMUL VLMUL = RISCVVType::getVLMUL(VTypeI);
StringRef LMUL;
switch (VLMUL) {
- case RISCVII::LMUL_1:
+ case RISCVVType::LMUL_1:
LMUL = "M1";
break;
- case RISCVII::LMUL_2:
+ case RISCVVType::LMUL_2:
LMUL = "M2";
break;
- case RISCVII::LMUL_4:
+ case RISCVVType::LMUL_4:
LMUL = "M4";
break;
- case RISCVII::LMUL_8:
+ case RISCVVType::LMUL_8:
LMUL = "M8";
break;
- case RISCVII::LMUL_F2:
+ case RISCVVType::LMUL_F2:
LMUL = "MF2";
break;
- case RISCVII::LMUL_F4:
+ case RISCVVType::LMUL_F4:
LMUL = "MF4";
break;
- case RISCVII::LMUL_F8:
+ case RISCVVType::LMUL_F8:
LMUL = "MF8";
break;
- case RISCVII::LMUL_RESERVED:
+ case RISCVVType::LMUL_RESERVED:
llvm_unreachable("Cannot create instrument for LMUL_RESERVED");
}
SmallVector<UniqueInstrument> Instruments;
@@ -166,7 +166,7 @@ RISCVInstrumentManager::createInstruments(const MCInst &Inst) {
}
static std::pair<uint8_t, uint8_t>
-getEEWAndEMUL(unsigned Opcode, RISCVII::VLMUL LMUL, uint8_t SEW) {
+getEEWAndEMUL(unsigned Opcode, RISCVVType::VLMUL LMUL, uint8_t SEW) {
uint8_t EEW;
switch (Opcode) {
case RISCV::VLM_V:
@@ -249,7 +249,7 @@ unsigned RISCVInstrumentManager::getSchedClassID(
const RISCVVInversePseudosTable::PseudoInfo *RVV = nullptr;
if (opcodeHasEEWAndEMULInfo(Opcode)) {
- RISCVII::VLMUL VLMUL = static_cast<RISCVII::VLMUL>(LMUL);
+ RISCVVType::VLMUL VLMUL = static_cast<RISCVVType::VLMUL>(LMUL);
auto [EEW, EMUL] = getEEWAndEMUL(Opcode, VLMUL, SEW);
RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, EMUL, EEW);
} else {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 2f4b569041a6f..58eb48ed613df 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -65,13 +65,9 @@ enum {
VLMulShift = ConstraintShift + 3,
VLMulMask = 0b111 << VLMulShift,
- // Force a tail agnostic policy even this instruction has a tied destination.
- ForceTailAgnosticShift = VLMulShift + 3,
- ForceTailAgnosticMask = 1 << ForceTailAgnosticShift,
-
// Is this a _TIED vector pseudo instruction. For these instructions we
// shouldn't skip the tied operand when converting to MC instructions.
- IsTiedPseudoShift = ForceTailAgnosticShift + 1,
+ IsTiedPseudoShift = VLMulShift + 3,
IsTiedPseudoMask = 1 << IsTiedPseudoShift,
// Does this instruction have a SEW operand. It will be the last explicit
@@ -145,12 +141,8 @@ static inline unsigned getFormat(uint64_t TSFlags) {
return (TSFlags & InstFormatMask) >> InstFormatShift;
}
/// \returns the LMUL for the instruction.
-static inline VLMUL getLMul(uint64_t TSFlags) {
- return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
-}
-/// \returns true if tail agnostic is enforced for the instruction.
-static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
- return TSFlags & ForceTailAgnosticMask;
+static inline RISCVVType::VLMUL getLMul(uint64_t TSFlags) {
+ return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
}
/// \returns true if this a _TIED pseudo.
static inline bool isTiedPseudo(uint64_t TSFlags) {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index d5254719b3839..a4a40862a67c6 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -210,7 +210,7 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
unsigned Imm = MI->getOperand(OpNo).getImm();
// Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx,
// or non-zero in bits 8 and above.
- if (RISCVVType::getVLMUL(Imm) == RISCVII::VLMUL::LMUL_RESERVED ||
+ if (RISCVVType::getVLMUL(Imm) == RISCVVType::VLMUL::LMUL_RESERVED ||
RISCVVType::getSEW(Imm) > 64 || (Imm >> 8) != 0) {
O << formatImm(Imm);
return;
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index fb2c5c62ef871..7ea4bd94c0065 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -279,7 +279,7 @@ void RISCVDAGToDAGISel::addVectorLoadStoreOperands(
// none of the others do. All have passthru operands. For our pseudos,
// all loads have policy operands.
if (IsLoad) {
- uint64_t Policy = RISCVII::MASK_AGNOSTIC;
+ uint64_t Policy = RISCVVType::MASK_AGNOSTIC;
if (IsMasked)
Policy = Node->getConstantOperandVal(CurOp++);
SDValue PolicyOp = CurDAG->getTargetConstant(Policy, DL, XLenVT);
@@ -294,7 +294,7 @@ void RISCVDAGToDAGISel::selectVLSEG(SDNode *Node, unsigned NF, bool IsMasked,
SDLoc DL(Node);
MVT VT = Node->getSimpleValueType(0);
unsigned Log2SEW = Node->getConstantOperandVal(Node->getNumOperands() - 1);
- RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
+ RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
unsigned CurOp = 2;
SmallVector<SDValue, 8> Operands;
@@ -324,7 +324,7 @@ void RISCVDAGToDAGISel::selectVLSEGFF(SDNode *Node, unsigned NF,
MVT VT = Node->getSimpleValueType(0);
MVT XLenVT = Subtarget->getXLenVT();
unsigned Log2SEW = Node->getConstantOperandVal(Node->getNumOperands() - 1);
- RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
+ RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
unsigned CurOp = 2;
SmallVector<SDValue, 7> Operands;
@@ -355,7 +355,7 @@ void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, unsigned NF, bool IsMasked,
SDLoc DL(Node);
MVT VT = Node->getSimpleValueType(0);
unsigned Log2SEW = Node->getConstantOperandVal(Node->getNumOperands() - 1);
- RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
+ RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
unsigned CurOp = 2;
SmallVector<SDValue, 8> Operands;
@@ -379,7 +379,7 @@ void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, unsigned NF, bool IsMasked,
"Element count mismatch");
#endif
- RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
+ RISCVVType::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());
if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
report_fatal_error("The V extension does not support EEW=64 for index "
@@ -404,7 +404,7 @@ void RISCVDAGToDAGISel::selectVSSEG(SDNode *Node, unsigned NF, bool IsMasked,
SDLoc DL(Node);
MVT VT = Node->getOperand(2)->getSimpleValueType(0);
unsigned Log2SEW = Node->getConstantOperandVal(Node->getNumOperands() - 1);
- RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
+ RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
unsigned CurOp = 2;
SmallVector<SDValue, 8> Operands;
@@ -430,7 +430,7 @@ void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, unsigned NF, bool IsMasked,
SDLoc DL(Node);
MVT VT = Node->getOperand(2)->getSimpleValueType(0);
unsigned Log2SEW = Node->getConstantOperandVal(Node->getNumOperands() - 1);
- RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
+ RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
unsigned CurOp = 2;
SmallVector<SDValue, 8> Operands;
@@ -454,7 +454,7 @@ void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, unsigned NF, bool IsMasked,
"Element count mismatch");
#endif
- RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
+ RISCVVType::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());
if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
report_fatal_error("The V extension does not support EEW=64 for index "
@@ -495,7 +495,7 @@ void RISCVDAGToDAGISel::selectVSETVLI(SDNode *Node) {
unsigned SEW =
RISCVVType::decodeVSEW(Node->getConstantOperandVal(Offset) & 0x7);
- RISCVII::VLMUL VLMul = static_cast<RISCVII::VLMUL>(
+ RISCVVType::VLMUL VLMul = static_cast<RISCVVType::VLMUL>(
Node->getConstantOperandVal(Offset + 1) & 0x7);
unsigned VTypeI = RISCVVType::encodeVTYPE(VLMul, SEW, /*TailAgnostic*/ true,
@@ -1672,7 +1672,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
default:
llvm_unreachable("Unexpected LMUL!");
#define CASE_VMSLT_OPCODES(lmulenum, suffix) \
- case RISCVII::VLMUL::lmulenum: \
+ case RISCVVType::lmulenum: \
VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix \
: RISCV::PseudoVMSLT_VX_##suffix; \
VMSGTOpcode = IsUnsigned ? RISCV::PseudoVMSGTU_VX_##suffix \
@@ -1692,7 +1692,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
default:
llvm_unreachable("Unexpected LMUL!");
#define CASE_VMNAND_VMSET_OPCODES(lmulenum, suffix) \
- case RISCVII::VLMUL::lmulenum: \
+ case RISCVVType::lmulenum: \
VMNANDOpcode = RISCV::PseudoVMNAND_MM_##suffix; \
VMSetOpcode = RISCV::PseudoVMSET_M_##suffix; \
break;
@@ -1768,7 +1768,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
default:
llvm_unreachable("Unexpected LMUL!");
#define CASE_VMSLT_OPCODES(lmulenum, suffix) \
- case RISCVII::VLMUL::lmulenum: \
+ case RISCVVType::lmulenum: \
VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix \
: RISCV::PseudoVMSLT_VX_##suffix; \
VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix##_MASK \
@@ -1790,7 +1790,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
default:
llvm_unreachable("Unexpected LMUL!");
#define CASE_VMXOR_VMANDN_VMOR_OPCODES(lmulenum, suffix) \
- case RISCVII::VLMUL::lmulenum: \
+ case RISCVVType::lmulenum: \
VMXOROpcode = RISCV::PseudoVMXOR_MM_##suffix; \
VMANDNOpcode = RISCV::PseudoVMANDN_MM_##suffix; \
VMOROpcode = RISCV::PseudoVMOR_MM_##suffix; \
@@ -1838,13 +1838,16 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
return;
}
+ SDValue PolicyOp =
+ CurDAG->getTargetConstant(RISCVVType::TAIL_AGNOSTIC, DL, XLenVT);
+
if (IsCmpConstant) {
SDValue Imm =
selectImm(CurDAG, SDLoc(Src2), XLenVT, CVal - 1, *Subtarget);
ReplaceNode(Node, CurDAG->getMachineNode(
VMSGTMaskOpcode, DL, VT,
- {MaskedOff, Src1, Imm, Mask, VL, SEW}));
+ {MaskedOff, Src1, Imm, Mask, VL, SEW, PolicyOp}));
return;
}
@@ -1853,10 +1856,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
// The result is mask undisturbed.
// We use the same instructions to emulate mask agnostic behavior, because
// the agnostic result can be either undisturbed or all 1.
- SDValue Cmp = SDValue(
- CurDAG->getMachineNode(VMSLTMaskOpcode, DL, VT,
- {MaskedOff, Src1, Src2, Mask, VL, SEW}),
- 0);
+ SDValue Cmp = SDValue(CurDAG->getMachineNode(VMSLTMaskOpcode, DL, VT,
+ {MaskedOff, Src1, Src2, Mask,
+ VL, SEW, PolicyOp}),
+ 0);
// vmxor.mm vd, vd, v0 is used to update active value.
ReplaceNode(Node, CurDAG->getMachineNode(VMXOROpcode, DL, VT,
{Cmp, Mask, VL, MaskSEW}));
@@ -2002,8 +2005,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() &&
"Element count mismatch");
- RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
- RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
+ RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
+ RISCVVType::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());
if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
report_fatal_error("The V extension does not support EEW=64 for index "
@@ -2055,7 +2058,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStrided,
Operands, /*IsLoad=*/true);
- RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
+ RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
const RISCV::VLEPseudo *P =
RISCV::getVLEPseudo(IsMasked, IsStrided, /*FF*/ false, Log2SEW,
static_cast<unsigned>(LMUL));
@@ -2082,7 +2085,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
/*IsStridedOrIndexed*/ false, Operands,
/*IsLoad=*/true);
- RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
+ RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
const RISCV::VLEPseudo *P =
RISCV::getVLEPseudo(IsMasked, /*Strided*/...
[truncated]
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Feb 18, 2025
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Feb 19, 2025
…n RISCVTargetParser.h. NFC (llvm#127585) The VLMUL and policy enums originally lived in RISCVBaseInfo.h in the backend which is where everything else in the RISCVII namespace is defined. RISCVTargetParser.h is used by much more of the compiler and it doesn't really make sense to have 2 different namespaces exposed. These enums are both associated with VTYPE so using the RISCVVType namespace seems like a good home for them.
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The VLMUL and policy enums originally lived in RISCVBaseInfo.h in the
backend which is where everything else in the RISCVII namespace is defined.
RISCVTargetParser.h is used by much more of the compiler and it
doesn't really make sense to have 2 different namespaces exposed.
These enums are both associated with VTYPE so using the RISCVVType
namespace seems like a good home for them.