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[RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (#123193)
XiangShan-KunMingHu is the third generation of Open-source high-performance RISC-V processor developed by Beijing Institute of Open Source Chip (BOSC) , and its latest version is V2R2. The KunMingHu manual is now available at https://github.com/OpenXiangShan/XiangShan-User-Guide/releases. It will be updated on the official XiangShan documentation site: https://docs.xiangshan.cc/zh-cn/latest You can find the corresponding ISA extension from the XiangShan Github repository: https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/Parameters.scala If you want to track the latest performance data of KunMingHu, please check XiangShan Biweekly: https://docs.xiangshan.cc/zh-cn/latest/blog This PR adds the processor definition for KunMingHu V2R2, developed by the XSCC team https://github.com/orgs/OpenXiangShan/teams/xscc. The scheduling model for XiangShan-KunMingHu V2R2 will be submitted in a subsequent PR. --------- Co-authored-by: Shenglin Tang <[email protected]> Co-authored-by: Xu, Zefan <[email protected]> Co-authored-by: Tang Haojin <[email protected]>
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‎clang/test/Driver/riscv-cpus.c

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// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
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// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-kunminghu | FileCheck -check-prefix=MCPU-XIANGSHAN-KUNMINGHU %s
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// MCPU-XIANGSHAN-KUNMINGHU: "-nostdsysteminc" "-target-cpu" "xiangshan-kunminghu"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+m"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+a"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+f"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+d"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+c"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+b"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+v"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+h"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zic64b"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbom"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbop"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicboz"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccamoa"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccif"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicclsm"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccrse"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicntr"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicond"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicsr"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zihintntl"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zacas"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zawrs"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfa"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfh"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zca"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zcb"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zcmop"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zba"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbb"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbc"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkb"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkc"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkx"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbs"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkn"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zks"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvbb"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64d"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64f"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64x"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvfh"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvkb"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvkt"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl128b"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sha"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shcounterenw"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shgatpa"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shtvala"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shvsatpa"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shvstvala"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shvstvecd"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smcsrind"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smdbltrp"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smmpm"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smnpm"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smrnmi"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smstateen"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sscofpmf"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sscsrind"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssdbltrp"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssnpm"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sspm"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssstateen"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssstrict"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sstc"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssu64xl"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+supm"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+svnapot"
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// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-abi" "lp64d"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck -check-prefix=MCPU-SPACEMIT-X60 %s
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// MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
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// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m"

‎clang/test/Misc/target-invalid-cpu-note/riscv.c

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// RISCV64-SAME: {{^}}, syntacore-scr7
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// RISCV64-SAME: {{^}}, tt-ascalon-d8
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// RISCV64-SAME: {{^}}, veyron-v1
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// RISCV64-SAME: {{^}}, xiangshan-kunminghu
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// RISCV64-SAME: {{^}}, xiangshan-nanhu
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// RISCV64-SAME: {{$}}
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// TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
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// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-d8
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// TUNE-RISCV64-SAME: {{^}}, veyron-v1
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// TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu
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// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
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// TUNE-RISCV64-SAME: {{^}}, generic
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// TUNE-RISCV64-SAME: {{^}}, generic-ooo

‎llvm/docs/ReleaseNotes.md

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* Adds assembler support for ``.option exact``, which disables automatic compression,
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and branch and linker relaxation. This can be disabled with ``.option noexact``,
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which is also the default.
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* `-mcpu=xiangshan-kunminghu` was added.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVProcessors.td

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TuneZExtWFusion,
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TuneShiftedZExtWFusion]>;
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def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
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NoSchedModel,
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!listconcat(RVA23S64Features,
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[FeatureStdExtZacas,
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FeatureStdExtZbc,
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FeatureStdExtZfh,
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FeatureStdExtZkn,
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FeatureStdExtZks,
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FeatureStdExtZvfh,
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FeatureStdExtSmaia,
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FeatureStdExtSmcsrind,
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FeatureStdExtSmdbltrp,
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FeatureStdExtSmmpm,
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FeatureStdExtSmnpm,
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FeatureStdExtSmrnmi,
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FeatureStdExtSmstateen,
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FeatureStdExtSsaia,
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FeatureStdExtSscsrind,
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FeatureStdExtSsdbltrp,
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FeatureStdExtSspm,
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FeatureStdExtSsstrict,
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FeatureStdExtZvl128b]),
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[TuneNoDefaultUnroll,
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TuneZExtHFusion,
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TuneZExtWFusion,
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TuneShiftedZExtWFusion]>;
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def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
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NoSchedModel,
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!listconcat(RVA22S64Features,

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