[RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 #123193

liliumShade · 2025-01-16T12:32:18Z

XiangShan-KunMingHu is the third generation of Open-source high-performance RISC-V processor developed by Beijing Institute of Open Source Chip (BOSC) , and its latest version is V2R2.

The KunMingHu manual is now available at https://github.com/OpenXiangShan/XiangShan-User-Guide/releases.
It will be updated on the official XiangShan documentation site: https://docs.xiangshan.cc/zh-cn/latest

You can find the corresponding ISA extension from the XiangShan Github repository: https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/Parameters.scala

If you want to track the latest performance data of KunMingHu, please check XiangShan Biweekly: https://docs.xiangshan.cc/zh-cn/latest/blog

This PR adds the processor definition for KunMingHu V2R2, developed by the XSCC team https://github.com/orgs/OpenXiangShan/teams/xscc.

The scheduling model for XiangShan-KunMingHu V2R2 will be submitted in a subsequent PR.

Co-Authored-By: Shenglin Tang <[email protected]> Co-Authored-By: Xu, Zefan <[email protected]> Co-Authored-By: Tang Haojin <[email protected]>

github-actions · 2025-01-16T12:32:36Z

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llvmbot · 2025-01-16T12:33:08Z

@llvm/pr-subscribers-clang
@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-clang-driver

Author: Chyaka (liliumShade)

Changes

XiangShan-KunMingHu is the third generation of Open-source high-performance RISC-V processor developed by Beijing Institute of Open Source Chip (BOSC) , and its latest version is V2R2.

The KunMingHu manual is now available at https://github.com/OpenXiangShan/XiangShan-User-Guide/releases.
It will be updated on the official XiangShan documentation site: https://docs.xiangshan.cc/zh-cn/latest

You can find the corresponding ISA extension from the XiangShan Github repository: https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/Parameters.scala

If you want to track the latest performance data of KunMingHu, please check XiangShan Biweekly: https://docs.xiangshan.cc/zh-cn/latest/blog

This PR adds the processor definition for KunMingHu V2R2, developed by the XSCC team https://github.com/orgs/OpenXiangShan/teams/xscc.

The scheduling model for XiangShan-KunMingHu V2R2 will be submitted in a subsequent PR.

Full diff: https://github.com/llvm/llvm-project/pull/123193.diff

4 Files Affected:

(modified) clang/test/Driver/riscv-cpus.c (+47)
(modified) clang/test/Misc/target-invalid-cpu-note/riscv.c (+2)
(modified) llvm/docs/ReleaseNotes.md (+1)
(modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+31)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index e97b6940662d9f..b9b27eec61c6f3 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,53 @@
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-kunminghu | FileCheck -check-prefix=MCPU-XIANGSHAN-KUNMINGHU %s
+// MCPU-XIANGSHAN-KUNMINGHU: "-nostdsysteminc" "-target-cpu" "xiangshan-kunminghu"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+m"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+a"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+f"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+d"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+c"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+v"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zic64b" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbom" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbop" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicboz" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccif" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicclsm" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccrse" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicntr" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicond" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicsr" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zacas" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfh" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zba" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbb" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbc"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkb" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkc" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkx" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkn" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zks" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvfh"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl128b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smcsrind"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smdbltrp"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smmpm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smnpm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smrnmi"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smstateen"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sscsrind"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssdbltrp"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sspm"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssstrict"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "-zawrs" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "-ziccamoa" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "-zihintntl" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-abi" "lp64d"
+
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck -check-prefix=MCPU-SPACEMIT-X60 %s
 // MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
 // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index fb54dcb5b3a93a..e9ed7ff4764775 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -45,6 +45,7 @@
 // RISCV64-SAME: {{^}}, syntacore-scr7
 // RISCV64-SAME: {{^}}, tt-ascalon-d8
 // RISCV64-SAME: {{^}}, veyron-v1
+// RISCV64-SAME: {{^}}, xiangshan-kunminghu
 // RISCV64-SAME: {{^}}, xiangshan-nanhu
 // RISCV64-SAME: {{$}}
 
@@ -94,6 +95,7 @@
 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
 // TUNE-RISCV64-SAME: {{^}}, tt-ascalon-d8
 // TUNE-RISCV64-SAME: {{^}}, veyron-v1
+// TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu
 // TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
 // TUNE-RISCV64-SAME: {{^}}, generic
 // TUNE-RISCV64-SAME: {{^}}, rocket
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 8f88b824f965aa..4a191bfbe594c7 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -199,6 +199,7 @@ Changes to the RISC-V Backend
 * `-mcpu=tt-ascalon-d8` was added.
 * `-mcpu=mips-p8700` was added.
 * `-mcpu=sifive-p550` was added.
+* `-mcpu=xiangshan-kunminghu` was added.
 * The `Zacas` extension is no longer marked as experimental.
 * Added Smdbltrp, Ssdbltrp extensions to -march.
 * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6dfed7ddeb9f63..2a434f30722804 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -553,6 +553,37 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                          NoSchedModel,
+                                          !listconcat(!listremove(RVA23S64Features,
+                                                      [FeatureStdExtZiccamoa,
+                                                      FeatureStdExtZihintntl,
+                                                      FeatureStdExtZawrs]),
+                                            [FeatureStdExtZicsr,
+                                            FeatureStdExtZacas,
+                                            FeatureStdExtZbc,
+                                            FeatureStdExtZfh,
+                                            FeatureStdExtZkn,
+                                            FeatureStdExtZks,
+                                            FeatureStdExtZvfh,
+                                            FeatureStdExtSmaia,
+                                            FeatureStdExtSmcsrind,
+                                            FeatureStdExtSmdbltrp,
+                                            FeatureStdExtSmmpm,
+                                            FeatureStdExtSmnpm,
+                                            FeatureStdExtSmrnmi,
+                                            FeatureStdExtSmstateen,
+                                            FeatureStdExtSsaia,
+                                            FeatureStdExtSscsrind,
+                                            FeatureStdExtSsdbltrp,
+                                            FeatureStdExtSspm,
+                                            FeatureStdExtSsstrict,
+                                            FeatureStdExtZvl128b]),
+                                           [TuneNoDefaultUnroll,
+                                            TuneZExtHFusion,
+                                            TuneZExtWFusion,
+                                            TuneShiftedZExtWFusion]>;
+
 def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
                                        NoSchedModel,
                                        !listconcat(RVA22S64Features,

llvm/lib/Target/RISCV/RISCVProcessors.td

Xiangshan-Kunminghu now compatible with RVA23S64 specification Co-Authored-By: Shenglin Tang <[email protected]> Co-Authored-By: Xu, Zefan <[email protected]> Co-Authored-By: Tang Haojin <[email protected]>

cyyself · 2025-04-08T08:19:34Z

I think some feature is missing in clang/test/Driver/riscv-cpus.c, such as "Zvbb".

Verify 24 target features for `-mcpu=xiangshan-kunminghu` including: - Standard extensions (h/zfa/zvbb/sstc/sscofpmf) - Vendor-specific extensions (shgatpa/shvsatpa/ssu64xl)

…nXiangShan/llvm-project into OpenXiangShan/KunMingHu-V2R2

liliumShade · 2025-04-16T04:36:56Z

I think some feature is missing in clang/test/Driver/riscv-cpus.c, such as "Zvbb".

Thanks for the review! We've added the Zvbb test case and extended validation for XIANGSHAN-KUNMINGHU CPU's target features (including privileged/custom extensions)

tclin914 · 2025-04-16T05:18:28Z

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -558,6 +558,34 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                            TuneZExtWFusion,
                                            TuneShiftedZExtWFusion]>;

+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                          NoSchedModel,


indentation alignment

This corrects whitespace alignment in the xiangshan-kunminghu part of RISCVProcessors.td.

…nXiangShan/llvm-project into OpenXiangShan/KunMingHu-V2R2

llvm/docs/ReleaseNotes.md

llvm/lib/Target/RISCV/RISCVProcessors.td

wangpc-pp · 2025-04-18T03:13:03Z

LGTM in general, but I have a question here: can you clarify the naming strategy? The name used in -mcpu is xiangshan-kunminghu, which corresponds to the V2R2 version now apparently. Then, will there be V2R3/V3R2/...? If so, what should we use in -mcpu?

liliumShade · 2025-04-18T10:04:53Z

LGTM in general, but I have a question here: can you clarify the naming strategy? The name used in -mcpu is xiangshan-kunminghu, which corresponds to the V2R2 version now apparently. Then, will there be V2R3/V3R2/...? If so, what should we use in -mcpu?

Thank you for raising this! To clarify: V2R2 is the current frozen version of kunminghu, the subsequent development in the plan will not affect the ISA string and pipeline.

If significant changes ever arise in a future major version (e.g., a hypothetical V3), we will introduce a new -mcpu name to reflect that divergence.

wangpc-pp

LGTM! Thanks for the insistence!

github-actions · 2025-04-21T02:07:06Z

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…23193) XiangShan-KunMingHu is the third generation of Open-source high-performance RISC-V processor developed by Beijing Institute of Open Source Chip (BOSC) , and its latest version is V2R2. The KunMingHu manual is now available at https://github.com/OpenXiangShan/XiangShan-User-Guide/releases. It will be updated on the official XiangShan documentation site: https://docs.xiangshan.cc/zh-cn/latest You can find the corresponding ISA extension from the XiangShan Github repository: https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/Parameters.scala If you want to track the latest performance data of KunMingHu, please check XiangShan Biweekly: https://docs.xiangshan.cc/zh-cn/latest/blog This PR adds the processor definition for KunMingHu V2R2, developed by the XSCC team https://github.com/orgs/OpenXiangShan/teams/xscc. The scheduling model for XiangShan-KunMingHu V2R2 will be submitted in a subsequent PR. --------- Co-authored-by: Shenglin Tang <[email protected]> Co-authored-by: Xu, Zefan <[email protected]> Co-authored-by: Tang Haojin <[email protected]>

[RISCV] Add processor definition for XiangShan-KunMingHu-V2R2

08f8115

Co-Authored-By: Shenglin Tang <[email protected]> Co-Authored-By: Xu, Zefan <[email protected]> Co-Authored-By: Tang Haojin <[email protected]>

llvmbot added clang Clang issues not falling into any other category backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' labels Jan 16, 2025

wangpc-pp reviewed Jan 16, 2025

View reviewed changes

llvm/lib/Target/RISCV/RISCVProcessors.td Outdated Show resolved Hide resolved

liliumShade and others added 2 commits February 7, 2025 11:12

Add "ziccamoa" "zihintntl" and "zawrs"

cefdeb0

Xiangshan-Kunminghu now compatible with RVA23S64 specification Co-Authored-By: Shenglin Tang <[email protected]> Co-Authored-By: Xu, Zefan <[email protected]> Co-Authored-By: Tang Haojin <[email protected]>

Merge branch 'main' into OpenXiangShan/KunMingHu-V2R2

07ef684

liliumShade added 3 commits April 16, 2025 11:13

Add XIANGSHAN-KUNMINGHU CPU test

24381ad

Verify 24 target features for `-mcpu=xiangshan-kunminghu` including: - Standard extensions (h/zfa/zvbb/sstc/sscofpmf) - Vendor-specific extensions (shgatpa/shvsatpa/ssu64xl)

Merge branch 'OpenXiangShan/KunMingHu-V2R2' of https://github.com/Ope…

b0a2ed3

…nXiangShan/llvm-project into OpenXiangShan/KunMingHu-V2R2

Merge branch 'main' into OpenXiangShan/KunMingHu-V2R2

0a5f67a

tclin914 reviewed Apr 16, 2025

View reviewed changes

liliumShade added 2 commits April 16, 2025 15:32

FIx indentation in RISCVProcessors.td

9b26bc0

This corrects whitespace alignment in the xiangshan-kunminghu part of RISCVProcessors.td.

Merge branch 'OpenXiangShan/KunMingHu-V2R2' of https://github.com/Ope…

edbfa6a

…nXiangShan/llvm-project into OpenXiangShan/KunMingHu-V2R2

wangpc-pp reviewed Apr 17, 2025

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llvm/docs/ReleaseNotes.md Outdated Show resolved Hide resolved

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liliumShade added 2 commits April 17, 2025 16:34

Remove blank line in ReleaseNotes.md

d438f24

Remove "FeatureStdExtZicsr" from RISCVProcessors.td

cca4fb2

wangpc-pp approved these changes Apr 18, 2025

View reviewed changes

Merge branch 'main' into OpenXiangShan/KunMingHu-V2R2

395b688

mshockwave approved these changes Apr 18, 2025

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Lancern merged commit 0e3e0bf into llvm:main Apr 21, 2025
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