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[RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 #123193

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Merged
merged 11 commits into from
Apr 21, 2025
Merged

[RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 #123193

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08f8115
[RISCV] Add processor definition for XiangShan-KunMingHu-V2R2
liliumShade Jan 16, 2025
cefdeb0
Add "ziccamoa" "zihintntl" and "zawrs"
liliumShade Feb 7, 2025
07ef684
Merge branch 'main' into OpenXiangShan/KunMingHu-V2R2
liliumShade Feb 7, 2025
24381ad
Add XIANGSHAN-KUNMINGHU CPU test
liliumShade Apr 16, 2025
b0a2ed3
Merge branch 'OpenXiangShan/KunMingHu-V2R2' of https://github.com/Ope…
liliumShade Apr 16, 2025
0a5f67a
Merge branch 'main' into OpenXiangShan/KunMingHu-V2R2
liliumShade Apr 16, 2025
9b26bc0
FIx indentation in RISCVProcessors.td
liliumShade Apr 16, 2025
edbfa6a
Merge branch 'OpenXiangShan/KunMingHu-V2R2' of https://github.com/Ope…
liliumShade Apr 16, 2025
d438f24
Remove blank line in ReleaseNotes.md
liliumShade Apr 17, 2025
cca4fb2
Remove "FeatureStdExtZicsr" from RISCVProcessors.td
liliumShade Apr 18, 2025
395b688
Merge branch 'main' into OpenXiangShan/KunMingHu-V2R2
liliumShade Apr 18, 2025
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72 changes: 72 additions & 0 deletions clang/test/Driver/riscv-cpus.c
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,78 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"

// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-kunminghu | FileCheck -check-prefix=MCPU-XIANGSHAN-KUNMINGHU %s
// MCPU-XIANGSHAN-KUNMINGHU: "-nostdsysteminc" "-target-cpu" "xiangshan-kunminghu"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+m"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+a"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+f"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+d"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+c"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+b"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+v"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+h"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zic64b"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbom"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbop"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicboz"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccamoa"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccif"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicclsm"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ziccrse"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicntr"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicond"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicsr"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zihintntl"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zacas"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zawrs"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfa"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zfh"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zca"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zcb"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zcmop"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zba"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbb"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbc"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkb"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkc"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkx"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbs"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkn"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zks"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvbb"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64d"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64f"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64x"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvfh"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvkb"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvkt"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl128b"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sha"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shcounterenw"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shgatpa"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shtvala"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shvsatpa"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shvstvala"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+shvstvecd"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smcsrind"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smdbltrp"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smmpm"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smnpm"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smrnmi"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+smstateen"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sscofpmf"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sscsrind"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssdbltrp"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssnpm"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sspm"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssstateen"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssstrict"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+sstc"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+ssu64xl"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+supm"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+svnapot"
// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-abi" "lp64d"

// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck -check-prefix=MCPU-SPACEMIT-X60 %s
// MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m"
Expand Down
2 changes: 2 additions & 0 deletions clang/test/Misc/target-invalid-cpu-note/riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,7 @@
// RISCV64-SAME: {{^}}, syntacore-scr7
// RISCV64-SAME: {{^}}, tt-ascalon-d8
// RISCV64-SAME: {{^}}, veyron-v1
// RISCV64-SAME: {{^}}, xiangshan-kunminghu
// RISCV64-SAME: {{^}}, xiangshan-nanhu
// RISCV64-SAME: {{$}}

Expand Down Expand Up @@ -95,6 +96,7 @@
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-d8
// TUNE-RISCV64-SAME: {{^}}, veyron-v1
// TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu
// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
// TUNE-RISCV64-SAME: {{^}}, generic
// TUNE-RISCV64-SAME: {{^}}, generic-ooo
Expand Down
1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.md
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Original file line number Diff line number Diff line change
Expand Up @@ -167,6 +167,7 @@ Changes to the RISC-V Backend
* Adds assembler support for ``.option exact``, which disables automatic compression,
and branch and linker relaxation. This can be disabled with ``.option noexact``,
which is also the default.
* `-mcpu=xiangshan-kunminghu` was added.

Changes to the WebAssembly Backend
----------------------------------
Expand Down
27 changes: 27 additions & 0 deletions llvm/lib/Target/RISCV/RISCVProcessors.td
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Original file line number Diff line number Diff line change
Expand Up @@ -558,6 +558,33 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;

def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
NoSchedModel,
!listconcat(RVA23S64Features,
[FeatureStdExtZacas,
FeatureStdExtZbc,
FeatureStdExtZfh,
FeatureStdExtZkn,
FeatureStdExtZks,
FeatureStdExtZvfh,
FeatureStdExtSmaia,
FeatureStdExtSmcsrind,
FeatureStdExtSmdbltrp,
FeatureStdExtSmmpm,
FeatureStdExtSmnpm,
FeatureStdExtSmrnmi,
FeatureStdExtSmstateen,
FeatureStdExtSsaia,
FeatureStdExtSscsrind,
FeatureStdExtSsdbltrp,
FeatureStdExtSspm,
FeatureStdExtSsstrict,
FeatureStdExtZvl128b]),
[TuneNoDefaultUnroll,
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;

def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
NoSchedModel,
!listconcat(RVA22S64Features,
Expand Down