clang format

jiahanxie353 · jiahanxie353 · commit 12ab39a40581 · 2024-01-31T14:30:31.000-05:00
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
@@ -281,7 +281,8 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
     }
 
     const LLT Ty = MRI.getType(VReg);
-    if (Ty.isValid() && TypeSize::isKnownGT(Ty.getSizeInBits(), TRI.getRegSizeInBits(*RC))) {
+    if (Ty.isValid() &&
+        TypeSize::isKnownGT(Ty.getSizeInBits(), TRI.getRegSizeInBits(*RC))) {
       reportGISelFailure(
           MF, TPC, MORE, "gisel-select",
           "VReg's low-level type and register class have different sizes", *MI);

Original file line number	Diff line number	Diff line change
`@@ -281,7 +281,8 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {`
`281`	`281`	`}`
`282`	`282`
`283`	`283`	`const LLT Ty = MRI.getType(VReg);`
`284`		`- if (Ty.isValid() && TypeSize::isKnownGT(Ty.getSizeInBits(), TRI.getRegSizeInBits(*RC))) {`
	`284`	`+ if (Ty.isValid() &&`
	`285`	`+ TypeSize::isKnownGT(Ty.getSizeInBits(), TRI.getRegSizeInBits(*RC))) {`
`285`	`286`	`reportGISelFailure(`
`286`	`287`	`MF, TPC, MORE, "gisel-select",`
`287`	`288`	`"VReg's low-level type and register class have different sizes", *MI);`