Skip to content

Commit 15faa57

Browse files
epilkepilk
committed
Address review comments
1 parent 954892f commit 15faa57

25 files changed

+68
-77
lines changed

‎llvm/docs/AMDGPUUsage.rst

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15416,9 +15416,9 @@ command-line options such as ``-triple``, ``-mcpu``, and
1541615416
The target ID syntax used for code object V2 to V3 for this directive differs
1541715417
from that used elsewhere. See :ref:`amdgpu-target-id-v2-v3`.
1541815418

15419-
.. _amdgpu-assembler-directive-amdgcn-code-object-version:
15419+
.. _amdgpu-assembler-directive-amdhsa-code-object-version:
1542015420

15421-
.amdgcn_code_object_version <version>
15421+
.amdhsa_code_object_version <version>
1542215422
+++++++++++++++++++++++++++++++++++++
1542315423

1542415424
Optional directive which declares the code object version to be generated by the

‎llvm/include/llvm/MC/MCAssembler.h

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -154,13 +154,12 @@ class MCAssembler {
154154
bool SubsectionsViaSymbols : 1;
155155
bool IncrementalLinkerCompatible : 1;
156156

157-
/// ELF specific e_header flags
158-
// It would be good if there were an MCELFAssembler class to hold this.
159-
// ELF header flags are used both by the integrated and standalone assemblers.
157+
/// ELF specific e_header and abi version flags
158+
// It would be good if there were an MCELFAssembler class to hold these. ELF
159+
// header flags are used both by the integrated and standalone assemblers.
160160
// Access to the flags is necessary in cases where assembler directives affect
161161
// which flags to be set.
162162
unsigned ELFHeaderEFlags;
163-
164163
unsigned char ELFHeaderABIVersion = 0;
165164

166165
/// Used to communicate Linker Optimization Hint information between

‎llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -117,16 +117,17 @@ void AMDGPUAsmPrinter::initTargetStreamer(Module &M) {
117117
if (getTargetStreamer() && !getTargetStreamer()->getTargetID())
118118
initializeTargetID(M);
119119

120-
getTargetStreamer()->EmitDirectiveAMDGCNCodeObjectVersion(CodeObjectVersion);
121-
122120
if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
123121
TM.getTargetTriple().getOS() != Triple::AMDPAL)
124122
return;
125123

126124
getTargetStreamer()->EmitDirectiveAMDGCNTarget();
127125

128-
if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
126+
if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
127+
getTargetStreamer()->EmitDirectiveAMDHSACodeObjectVersion(
128+
CodeObjectVersion);
129129
HSAMetadataStream->begin(M, *getTargetStreamer()->getTargetID());
130+
}
130131

131132
if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
132133
getTargetStreamer()->getPALMetadata()->readFromIR(M);
@@ -324,7 +325,7 @@ void AMDGPUAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
324325
}
325326

326327
bool AMDGPUAsmPrinter::doInitialization(Module &M) {
327-
CodeObjectVersion = AMDGPU::getCodeObjectVersion(M);
328+
CodeObjectVersion = AMDGPU::getAMDHSACodeObjectVersion(M);
328329

329330
if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
330331
switch (CodeObjectVersion) {

‎llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,7 @@ class AMDGPUInformationCache : public InformationCache {
144144
BumpPtrAllocator &Allocator,
145145
SetVector<Function *> *CGSCC, TargetMachine &TM)
146146
: InformationCache(M, AG, Allocator, CGSCC), TM(TM),
147-
CodeObjectVersion(AMDGPU::getCodeObjectVersion(M)) {}
147+
CodeObjectVersion(AMDGPU::getAMDHSACodeObjectVersion(M)) {}
148148

149149
TargetMachine &TM;
150150

‎llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -474,7 +474,7 @@ static void allocateHSAUserSGPRs(CCState &CCInfo,
474474

475475
const Module *M = MF.getFunction().getParent();
476476
if (UserSGPRInfo.hasQueuePtr() &&
477-
AMDGPU::getCodeObjectVersion(*M) < AMDGPU::AMDHSA_COV5) {
477+
AMDGPU::getAMDHSACodeObjectVersion(*M) < AMDGPU::AMDHSA_COV5) {
478478
Register QueuePtrReg = Info.addQueuePtr(TRI);
479479
MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
480480
CCInfo.AllocateReg(QueuePtrReg);

‎llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -532,7 +532,8 @@ void MetadataStreamerMsgPackV4::emitKernel(const MachineFunction &MF,
532532
Func.getCallingConv() != CallingConv::SPIR_KERNEL)
533533
return;
534534

535-
auto CodeObjectVersion = AMDGPU::getCodeObjectVersion(*Func.getParent());
535+
auto CodeObjectVersion =
536+
AMDGPU::getAMDHSACodeObjectVersion(*Func.getParent());
536537
auto Kern = getHSAKernelProps(MF, ProgramInfo, CodeObjectVersion);
537538

538539
auto Kernels =

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2128,7 +2128,7 @@ Register AMDGPULegalizerInfo::getSegmentAperture(
21282128
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
21292129
// For code object version 5, private_base and shared_base are passed through
21302130
// implicit kernargs.
2131-
if (AMDGPU::getCodeObjectVersion(*MF.getFunction().getParent()) >=
2131+
if (AMDGPU::getAMDHSACodeObjectVersion(*MF.getFunction().getParent()) >=
21322132
AMDGPU::AMDHSA_COV5) {
21332133
AMDGPUTargetLowering::ImplicitParameter Param =
21342134
AS == AMDGPUAS::LOCAL_ADDRESS ? AMDGPUTargetLowering::SHARED_BASE
@@ -6534,7 +6534,7 @@ bool AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr(
65346534

65356535
Register SGPR01(AMDGPU::SGPR0_SGPR1);
65366536
// For code object version 5, queue_ptr is passed through implicit kernarg.
6537-
if (AMDGPU::getCodeObjectVersion(*MF.getFunction().getParent()) >=
6537+
if (AMDGPU::getAMDHSACodeObjectVersion(*MF.getFunction().getParent()) >=
65386538
AMDGPU::AMDHSA_COV5) {
65396539
AMDGPUTargetLowering::ImplicitParameter Param =
65406540
AMDGPUTargetLowering::QUEUE_PTR;

‎llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -323,7 +323,8 @@ static bool processUse(CallInst *CI, bool IsV5OrAbove) {
323323
// TargetPassConfig for subtarget.
324324
bool AMDGPULowerKernelAttributes::runOnModule(Module &M) {
325325
bool MadeChange = false;
326-
bool IsV5OrAbove = AMDGPU::getCodeObjectVersion(M) >= AMDGPU::AMDHSA_COV5;
326+
bool IsV5OrAbove =
327+
AMDGPU::getAMDHSACodeObjectVersion(M) >= AMDGPU::AMDHSA_COV5;
327328
Function *BasePtr = getBasePtrIntrinsic(M, IsV5OrAbove);
328329

329330
if (!BasePtr) // ImplicitArgPtr/DispatchPtr not used.
@@ -356,7 +357,7 @@ ModulePass *llvm::createAMDGPULowerKernelAttributesPass() {
356357
PreservedAnalyses
357358
AMDGPULowerKernelAttributesPass::run(Function &F, FunctionAnalysisManager &AM) {
358359
bool IsV5OrAbove =
359-
AMDGPU::getCodeObjectVersion(*F.getParent()) >= AMDGPU::AMDHSA_COV5;
360+
AMDGPU::getAMDHSACodeObjectVersion(*F.getParent()) >= AMDGPU::AMDHSA_COV5;
360361
Function *BasePtr = getBasePtrIntrinsic(*F.getParent(), IsV5OrAbove);
361362

362363
if (!BasePtr) // ImplicitArgPtr/DispatchPtr not used.

‎llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ bool AMDGPUResourceUsageAnalysis::runOnModule(Module &M) {
112112

113113
// By default, for code object v5 and later, track only the minimum scratch
114114
// size
115-
if (AMDGPU::getCodeObjectVersion(M) >= AMDGPU::AMDHSA_COV5 ||
115+
if (AMDGPU::getAMDHSACodeObjectVersion(M) >= AMDGPU::AMDHSA_COV5 ||
116116
STI.getTargetTriple().getOS() == Triple::AMDPAL) {
117117
if (!AssumedStackSizeForDynamicSizeObjects.getNumOccurrences())
118118
AssumedStackSizeForDynamicSizeObjects = 0;

‎llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -571,7 +571,7 @@ unsigned AMDGPUSubtarget::getImplicitArgNumBytes(const Function &F) const {
571571
// Assume all implicit inputs are used by default
572572
const Module *M = F.getParent();
573573
unsigned NBytes =
574-
AMDGPU::getCodeObjectVersion(*M) >= AMDGPU::AMDHSA_COV5 ? 256 : 56;
574+
AMDGPU::getAMDHSACodeObjectVersion(*M) >= AMDGPU::AMDHSA_COV5 ? 256 : 56;
575575
return F.getFnAttributeAsParsedInteger("amdgpu-implicitarg-num-bytes",
576576
NBytes);
577577
}

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1295,7 +1295,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
12951295
unsigned NextFreeSGPR, SMRange SGPRRange,
12961296
unsigned &VGPRBlocks, unsigned &SGPRBlocks);
12971297
bool ParseDirectiveAMDGCNTarget();
1298-
bool ParseDirectiveAMDGCNCodeObjectVersion();
1298+
bool ParseDirectiveAMDHSACodeObjectVersion();
12991299
bool ParseDirectiveAMDHSAKernel();
13001300
bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);
13011301
bool ParseDirectiveAMDKernelCodeT();
@@ -5526,12 +5526,12 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
55265526
return false;
55275527
}
55285528

5529-
bool AMDGPUAsmParser::ParseDirectiveAMDGCNCodeObjectVersion() {
5529+
bool AMDGPUAsmParser::ParseDirectiveAMDHSACodeObjectVersion() {
55305530
uint32_t Version;
55315531
if (ParseAsAbsoluteExpression(Version))
55325532
return true;
55335533

5534-
getTargetStreamer().EmitDirectiveAMDGCNCodeObjectVersion(Version);
5534+
getTargetStreamer().EmitDirectiveAMDHSACodeObjectVersion(Version);
55355535
return false;
55365536
}
55375537

@@ -5818,6 +5818,9 @@ bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
58185818
if (IDVal == ".amdhsa_kernel")
58195819
return ParseDirectiveAMDHSAKernel();
58205820

5821+
if (IDVal == ".amdhsa_code_object_version")
5822+
return ParseDirectiveAMDHSACodeObjectVersion();
5823+
58215824
// TODO: Restructure/combine with PAL metadata directive.
58225825
if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin)
58235826
return ParseDirectiveHSAMetadata();
@@ -5851,9 +5854,6 @@ bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
58515854
if (IDVal == PALMD::AssemblerDirective)
58525855
return ParseDirectivePALMetadata();
58535856

5854-
if (IDVal == ".amdgcn_code_object_version")
5855-
return ParseDirectiveAMDGCNCodeObjectVersion();
5856-
58575857
return true;
58585858
}
58595859

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2174,7 +2174,8 @@ AMDGPUDisassembler::decodeKernelDescriptorDirective(
21742174
KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
21752175
}
21762176

2177-
if (AMDGPU::getDefaultCodeObjectVersion() >= AMDGPU::AMDHSA_COV5)
2177+
// FIXME: We should be looking at the ELF header ABI version for this.
2178+
if (AMDGPU::getDefaultAMDHSACodeObjectVersion() >= AMDGPU::AMDHSA_COV5)
21782179
PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack",
21792180
KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
21802181

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -217,10 +217,10 @@ void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() {
217217
OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n";
218218
}
219219

220-
void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNCodeObjectVersion(
220+
void AMDGPUTargetAsmStreamer::EmitDirectiveAMDHSACodeObjectVersion(
221221
unsigned COV) {
222-
AMDGPUTargetStreamer::EmitDirectiveAMDGCNCodeObjectVersion(COV);
223-
OS << "\t.amdgcn_code_object_version " << COV << '\n';
222+
AMDGPUTargetStreamer::EmitDirectiveAMDHSACodeObjectVersion(COV);
223+
OS << "\t.amdhsa_code_object_version " << COV << '\n';
224224
}
225225

226226
void

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -44,15 +44,15 @@ class AMDGPUTargetStreamer : public MCTargetStreamer {
4444
public:
4545
AMDGPUTargetStreamer(MCStreamer &S)
4646
: MCTargetStreamer(S),
47-
// Assume the default COV for now, EmitDirectiveAMDGCNCodeObjectVersion
47+
// Assume the default COV for now, EmitDirectiveAMDHSACodeObjectVersion
4848
// will update this if it is encountered.
49-
CodeObjectVersion(AMDGPU::getDefaultCodeObjectVersion()) {}
49+
CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) {}
5050

5151
AMDGPUPALMetadata *getPALMetadata() { return &PALMetadata; }
5252

5353
virtual void EmitDirectiveAMDGCNTarget(){};
5454

55-
virtual void EmitDirectiveAMDGCNCodeObjectVersion(unsigned COV) {
55+
virtual void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV) {
5656
CodeObjectVersion = COV;
5757
}
5858

@@ -128,7 +128,7 @@ class AMDGPUTargetAsmStreamer final : public AMDGPUTargetStreamer {
128128

129129
void EmitDirectiveAMDGCNTarget() override;
130130

131-
void EmitDirectiveAMDGCNCodeObjectVersion(unsigned COV) override;
131+
void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV) override;
132132

133133
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override;
134134

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2211,7 +2211,7 @@ void SITargetLowering::allocateSpecialInputSGPRs(
22112211

22122212
const Module *M = MF.getFunction().getParent();
22132213
if (UserSGPRInfo.hasQueuePtr() &&
2214-
AMDGPU::getCodeObjectVersion(*M) < AMDGPU::AMDHSA_COV5)
2214+
AMDGPU::getAMDHSACodeObjectVersion(*M) < AMDGPU::AMDHSA_COV5)
22152215
allocateSGPR64Input(CCInfo, ArgInfo.QueuePtr);
22162216

22172217
// Implicit arg ptr takes the place of the kernarg segment pointer. This is a
@@ -2264,7 +2264,7 @@ void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,
22642264

22652265
const Module *M = MF.getFunction().getParent();
22662266
if (UserSGPRInfo.hasQueuePtr() &&
2267-
AMDGPU::getCodeObjectVersion(*M) < AMDGPU::AMDHSA_COV5) {
2267+
AMDGPU::getAMDHSACodeObjectVersion(*M) < AMDGPU::AMDHSA_COV5) {
22682268
Register QueuePtrReg = Info.addQueuePtr(TRI);
22692269
MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
22702270
CCInfo.AllocateReg(QueuePtrReg);
@@ -6176,7 +6176,7 @@ SDValue SITargetLowering::lowerTrapHsaQueuePtr(
61766176
SDValue QueuePtr;
61776177
// For code object version 5, QueuePtr is passed through implicit kernarg.
61786178
const Module *M = DAG.getMachineFunction().getFunction().getParent();
6179-
if (AMDGPU::getCodeObjectVersion(*M) >= AMDGPU::AMDHSA_COV5) {
6179+
if (AMDGPU::getAMDHSACodeObjectVersion(*M) >= AMDGPU::AMDHSA_COV5) {
61806180
QueuePtr =
61816181
loadImplicitKernelArgument(DAG, MVT::i64, SL, Align(8), QUEUE_PTR);
61826182
} else {
@@ -6280,7 +6280,7 @@ SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
62806280
// For code object version 5, private_base and shared_base are passed through
62816281
// implicit kernargs.
62826282
const Module *M = DAG.getMachineFunction().getFunction().getParent();
6283-
if (AMDGPU::getCodeObjectVersion(*M) >= AMDGPU::AMDHSA_COV5) {
6283+
if (AMDGPU::getAMDHSACodeObjectVersion(*M) >= AMDGPU::AMDHSA_COV5) {
62846284
ImplicitParameter Param =
62856285
(AS == AMDGPUAS::LOCAL_ADDRESS) ? SHARED_BASE : PRIVATE_BASE;
62866286
return loadImplicitKernelArgument(DAG, MVT::i32, DL, Align(4), Param);

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -124,16 +124,16 @@ bool isHsaAbi(const MCSubtargetInfo &STI) {
124124
return STI.getTargetTriple().getOS() == Triple::AMDHSA;
125125
}
126126

127-
unsigned getCodeObjectVersion(const Module &M) {
127+
unsigned getAMDHSACodeObjectVersion(const Module &M) {
128128
if (auto Ver = mdconst::extract_or_null<ConstantInt>(
129129
M.getModuleFlag("amdgpu_code_object_version"))) {
130130
return (unsigned)Ver->getZExtValue() / 100;
131131
}
132132

133-
return getDefaultCodeObjectVersion();
133+
return getDefaultAMDHSACodeObjectVersion();
134134
}
135135

136-
unsigned getDefaultCodeObjectVersion() {
136+
unsigned getDefaultAMDHSACodeObjectVersion() {
137137
return DefaultAMDHSACodeObjectVersion;
138138
}
139139

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -48,15 +48,15 @@ enum { AMDHSA_COV4 = 4, AMDHSA_COV5 = 5 };
4848
bool isHsaAbi(const MCSubtargetInfo &STI);
4949

5050
/// \returns Code object version from the IR module flag.
51-
unsigned getCodeObjectVersion(const Module &M);
51+
unsigned getAMDHSACodeObjectVersion(const Module &M);
5252

53-
/// \returns The default code object version. This should only be used when we
54-
/// lack a more accurate CodeObjectVersion value (e.g. from the IR module flag
55-
/// or a .amdgcn_code_object_version directive)
56-
unsigned getDefaultCodeObjectVersion();
53+
/// \returns The default HSA code object version. This should only be used when
54+
/// we lack a more accurate CodeObjectVersion value (e.g. from the IR module
55+
/// flag or a .amdhsa_code_object_version directive)
56+
unsigned getDefaultAMDHSACodeObjectVersion();
5757

58-
/// \returns ABIVersion suitable for use in ELF's e_ident[ABIVERSION].
59-
/// \param CodeObjectVersion is a value returned by getCodeObjectVersion().
58+
/// \returns ABIVersion suitable for use in ELF's e_ident[ABIVERSION]. \param
59+
/// CodeObjectVersion is a value returned by getAMDHSACodeObjectVersion().
6060
uint8_t getELFABIVersion(const Triple &OS, unsigned CodeObjectVersion);
6161

6262
/// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr

‎llvm/test/CodeGen/AMDGPU/code-object-v3.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefixes=ALL-ASM,OSABI-AMDHSA-ASM %s
22
; RUN: llc -filetype=obj -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | llvm-readelf -S -r -s --notes - | FileCheck --check-prefix=OSABI-AMDHSA-ELF %s
33

4-
; ALL-ASM: amdgcn_code_object_version 4
4+
; ALL-ASM: amdhsa_code_object_version 4
55

66
; ALL-ASM-LABEL: {{^}}fadd:
77

‎llvm/test/CodeGen/AMDGPU/codegen-internal-only-func.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,9 @@
88

99
; OPT: .text
1010
; OPT-NEXT: .section ".note.GNU-stack"
11-
; COV4-NEXT: .amdgcn_code_object_version 4
12-
; COV5-NEXT: .amdgcn_code_object_version 5
1311
; OPT-NEXT: .amdgcn_target "amdgcn-amd-amdhsa--gfx900"
12+
; COV4-NEXT: .amdhsa_code_object_version 4
13+
; COV5-NEXT: .amdhsa_code_object_version 5
1414
; OPT-NEXT: .amdgpu_metadata
1515
; OPT-NEXT: ---
1616
; OPT-NEXT: amdhsa.kernels: []

‎llvm/test/MC/AMDGPU/elf-header-cov.s

Lines changed: 1 addition & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -4,28 +4,10 @@
44
// RUN: sed 's/COV/5/g' %s | llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj | \
55
// RUN: llvm-readobj --file-headers - | FileCheck %s --check-prefixes=HS5
66

7-
// RUN: sed 's/COV/4/g' %s | llvm-mc -triple amdgcn-amd-amdpal -mcpu=gfx802 -filetype=obj | \
8-
// RUN: llvm-readobj --file-headers - | FileCheck %s --check-prefixes=PAL
9-
10-
// RUN: sed 's/COV/4/g' %s | llvm-mc -triple amdgcn-amd-mesa3d -mcpu=gfx802 -filetype=obj | \
11-
// RUN: llvm-readobj --file-headers - | FileCheck %s --check-prefixes=MSA
12-
13-
// RUN: sed 's/COV/4/g' %s | llvm-mc -triple amdgcn-amd- -mcpu=gfx802 -filetype=obj | \
14-
// RUN: llvm-readobj --file-headers - | FileCheck %s --check-prefixes=UNK
15-
16-
.amdgcn_code_object_version COV
7+
.amdhsa_code_object_version COV
178

189
// HS4: OS/ABI: AMDGPU_HSA (0x40)
1910
// HS4-NEXT: ABIVersion: 2
2011

2112
// HS5: OS/ABI: AMDGPU_HSA (0x40)
2213
// HS5-NEXT: ABIVersion: 3
23-
24-
// PAL: OS/ABI: AMDGPU_PAL (0x41)
25-
// PAL-NEXT: ABIVersion: 0
26-
27-
// MSA: OS/ABI: AMDGPU_MESA3D (0x42)
28-
// MSA-NEXT: ABIVersion: 0
29-
30-
// UNK: OS/ABI: SystemV (0x0)
31-
// UNK-NEXT: ABIVersion: 0

‎llvm/test/MC/AMDGPU/hsa-cov-invalid.s

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
// RUN: not llvm-mc -triple amdgcn-amd-amdpal -mcpu=gfx802 %s 2>&1 | FileCheck %s
2+
// RUN: not llvm-mc -triple amdgcn-amd-mesa3d -mcpu=gfx802 %s 2>&1 | FileCheck %s
3+
// RUN: not llvm-mc -triple amdgcn-amd- -mcpu=gfx802 %s 2>&1 | FileCheck %s
4+
5+
// CHECK: error: unknown directive
6+
.amdhsa_code_object_version 4

‎llvm/test/MC/AMDGPU/hsa-exp.s

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,8 +19,8 @@
1919
.amdgcn_target "amdgcn-unknown-amdhsa--gfx700"
2020
// ASM: .amdgcn_target "amdgcn-unknown-amdhsa--gfx700"
2121

22-
.amdgcn_code_object_version 4
23-
// ASM: .amdgcn_code_object_version 4
22+
.amdhsa_code_object_version 4
23+
// ASM: .amdhsa_code_object_version 4
2424

2525
.set my_is_ptr64, 1
2626

‎llvm/test/MC/AMDGPU/hsa-gfx12-v4.s

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -52,8 +52,8 @@
5252
.amdgcn_target "amdgcn-amd-amdhsa--gfx1200"
5353
// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx1200"
5454

55-
.amdgcn_code_object_version 4
56-
// ASM: .amdgcn_code_object_version 4
55+
.amdhsa_code_object_version 4
56+
// ASM: .amdhsa_code_object_version 4
5757

5858
.p2align 8
5959
.type minimal,@function

0 commit comments

Comments
 (0)