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llvm/utils/gn/secondary/llvm
include/llvm/TargetParser Expand file tree Collapse file tree 2 files changed +9
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lines changed Original file line number Diff line number Diff line change @@ -14,6 +14,13 @@ tablegen("AArch64TargetParserDef") {
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tblgen_target = " //llvm/utils/TableGen:llvm-min-tblgen"
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}
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+ tablegen (" PPCGenTargetFeatures" ) {
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+ visibility = [ " :gen" ]
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+ args = [ " -gen-target-features" ]
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+ td_file = " //llvm/lib/Target/PowerPC/PPC.td"
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+ tblgen_target = " //llvm/utils/TableGen:llvm-min-tblgen"
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+ }
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+
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tablegen (" RISCVTargetParserDef" ) {
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visibility = [ " :gen" ]
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args = [ " -gen-riscv-target-def" ]
@@ -25,6 +32,7 @@ group("gen") {
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deps = [
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" :AArch64TargetParserDef" ,
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" :ARMTargetParserDef" ,
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+ " :PPCGenTargetFeatures" ,
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" :RISCVTargetParserDef" ,
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]
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}
Original file line number Diff line number Diff line change @@ -12,6 +12,7 @@ source_set("Basic") {
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" RISCVTargetDefEmitter.cpp" ,
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" SDNodeProperties.cpp" ,
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" TableGen.cpp" ,
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+ " TargetFeaturesEmitter.cpp" ,
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" VTEmitter.cpp" ,
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]
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}
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