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[X86] Add missing immediate qualifier to the (V)PINSR/PEXTR instruction names
Makes it easier to algorithmically recreate the instruction name in various analysis scripts I'm working on
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9 files changed

+152
-152
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9 files changed

+152
-152
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‎llvm/lib/Target/X86/X86InstrAVX512.td

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -11432,7 +11432,7 @@ defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
1143211432

1143311433
multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
1143411434
X86VectorVTInfo _> {
11435-
def mr : AVX512Ii8<opc, MRMDestMem, (outs),
11435+
def mri : AVX512Ii8<opc, MRMDestMem, (outs),
1143611436
(ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
1143711437
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1143811438
[(store (_.EltVT (trunc (OpNode (_.VT _.RC:$src1), timm:$src2))),
@@ -11442,7 +11442,7 @@ multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
1144211442

1144311443
multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
1144411444
let Predicates = [HasBWI] in {
11445-
def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
11445+
def rri : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
1144611446
(ins _.RC:$src1, u8imm:$src2),
1144711447
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1144811448
[(set GR32orGR64:$dst,
@@ -11455,15 +11455,15 @@ multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
1145511455

1145611456
multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
1145711457
let Predicates = [HasBWI] in {
11458-
def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
11458+
def rri : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
1145911459
(ins _.RC:$src1, u8imm:$src2),
1146011460
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1146111461
[(set GR32orGR64:$dst,
1146211462
(X86pextrw (_.VT _.RC:$src1), timm:$src2))]>,
1146311463
EVEX, TB, PD, Sched<[WriteVecExtract]>;
1146411464

1146511465
let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in
11466-
def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
11466+
def rri_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
1146711467
(ins _.RC:$src1, u8imm:$src2),
1146811468
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1146911469
EVEX, TA, PD, Sched<[WriteVecExtract]>;
@@ -11475,14 +11475,14 @@ multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
1147511475
multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
1147611476
RegisterClass GRC> {
1147711477
let Predicates = [HasDQI] in {
11478-
def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
11478+
def rri : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
1147911479
(ins _.RC:$src1, u8imm:$src2),
1148011480
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1148111481
[(set GRC:$dst,
1148211482
(extractelt (_.VT _.RC:$src1), imm:$src2))]>,
1148311483
EVEX, TA, PD, Sched<[WriteVecExtract]>;
1148411484

11485-
def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
11485+
def mri : AVX512Ii8<0x16, MRMDestMem, (outs),
1148611486
(ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
1148711487
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1148811488
[(store (extractelt (_.VT _.RC:$src1),
@@ -11500,7 +11500,7 @@ defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, REX_W;
1150011500
multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
1150111501
X86VectorVTInfo _, PatFrag LdFrag,
1150211502
SDPatternOperator immoperator> {
11503-
def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
11503+
def rmi : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
1150411504
(ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
1150511505
OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1150611506
[(set _.RC:$dst,
@@ -11511,7 +11511,7 @@ multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
1151111511
multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
1151211512
X86VectorVTInfo _, PatFrag LdFrag> {
1151311513
let Predicates = [HasBWI] in {
11514-
def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
11514+
def rri : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
1151511515
(ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
1151611516
OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1151711517
[(set _.RC:$dst,
@@ -11525,7 +11525,7 @@ multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
1152511525
multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
1152611526
X86VectorVTInfo _, RegisterClass GRC> {
1152711527
let Predicates = [HasDQI] in {
11528-
def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
11528+
def rri : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
1152911529
(ins _.RC:$src1, GRC:$src2, u8imm:$src3),
1153011530
OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1153111531
[(set _.RC:$dst,
@@ -11548,27 +11548,27 @@ let Predicates = [HasAVX512, NoBWI] in {
1154811548
def : Pat<(X86pinsrb VR128:$src1,
1154911549
(i32 (anyext (i8 (bitconvert v8i1:$src2)))),
1155011550
timm:$src3),
11551-
(VPINSRBrr VR128:$src1, (i32 (COPY_TO_REGCLASS VK8:$src2, GR32)),
11552-
timm:$src3)>;
11551+
(VPINSRBrri VR128:$src1, (i32 (COPY_TO_REGCLASS VK8:$src2, GR32)),
11552+
timm:$src3)>;
1155311553
}
1155411554

1155511555
let Predicates = [HasBWI] in {
1155611556
def : Pat<(X86pinsrb VR128:$src1, (i32 (anyext (i8 GR8:$src2))), timm:$src3),
11557-
(VPINSRBZrr VR128:$src1, (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
11558-
GR8:$src2, sub_8bit), timm:$src3)>;
11557+
(VPINSRBZrri VR128:$src1, (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
11558+
GR8:$src2, sub_8bit), timm:$src3)>;
1155911559
def : Pat<(X86pinsrb VR128:$src1,
1156011560
(i32 (anyext (i8 (bitconvert v8i1:$src2)))),
1156111561
timm:$src3),
11562-
(VPINSRBZrr VR128:$src1, (i32 (COPY_TO_REGCLASS VK8:$src2, GR32)),
11563-
timm:$src3)>;
11562+
(VPINSRBZrri VR128:$src1, (i32 (COPY_TO_REGCLASS VK8:$src2, GR32)),
11563+
timm:$src3)>;
1156411564
}
1156511565

1156611566
// Always select FP16 instructions if available.
1156711567
let Predicates = [HasBWI], AddedComplexity = -10 in {
11568-
def : Pat<(f16 (load addr:$src)), (COPY_TO_REGCLASS (VPINSRWZrm (v8i16 (IMPLICIT_DEF)), addr:$src, 0), FR16X)>;
11569-
def : Pat<(store f16:$src, addr:$dst), (VPEXTRWZmr addr:$dst, (v8i16 (COPY_TO_REGCLASS FR16:$src, VR128)), 0)>;
11570-
def : Pat<(i16 (bitconvert f16:$src)), (EXTRACT_SUBREG (VPEXTRWZrr (v8i16 (COPY_TO_REGCLASS FR16X:$src, VR128X)), 0), sub_16bit)>;
11571-
def : Pat<(f16 (bitconvert i16:$src)), (COPY_TO_REGCLASS (VPINSRWZrr (v8i16 (IMPLICIT_DEF)), (INSERT_SUBREG (IMPLICIT_DEF), GR16:$src, sub_16bit), 0), FR16X)>;
11568+
def : Pat<(f16 (load addr:$src)), (COPY_TO_REGCLASS (VPINSRWZrmi (v8i16 (IMPLICIT_DEF)), addr:$src, 0), FR16X)>;
11569+
def : Pat<(store f16:$src, addr:$dst), (VPEXTRWZmri addr:$dst, (v8i16 (COPY_TO_REGCLASS FR16:$src, VR128)), 0)>;
11570+
def : Pat<(i16 (bitconvert f16:$src)), (EXTRACT_SUBREG (VPEXTRWZrri (v8i16 (COPY_TO_REGCLASS FR16X:$src, VR128X)), 0), sub_16bit)>;
11571+
def : Pat<(f16 (bitconvert i16:$src)), (COPY_TO_REGCLASS (VPINSRWZrri (v8i16 (IMPLICIT_DEF)), (INSERT_SUBREG (IMPLICIT_DEF), GR16:$src, sub_16bit), 0), FR16X)>;
1157211572
}
1157311573

1157411574
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/X86/X86InstrMMX.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -509,23 +509,23 @@ let Constraints = "$src1 = $dst" in {
509509

510510
// Extract / Insert
511511
let Predicates = [HasMMX, HasSSE1] in
512-
def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg,
512+
def MMX_PEXTRWrri : MMXIi8<0xC5, MRMSrcReg,
513513
(outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2),
514514
"pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
515515
[(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1,
516516
timm:$src2))]>,
517517
Sched<[WriteVecExtract]>;
518518
let Constraints = "$src1 = $dst" in {
519519
let Predicates = [HasMMX, HasSSE1] in {
520-
def MMX_PINSRWrr : MMXIi8<0xC4, MRMSrcReg,
520+
def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
521521
(outs VR64:$dst),
522522
(ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
523523
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
524524
[(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
525525
GR32orGR64:$src2, timm:$src3))]>,
526526
Sched<[WriteVecInsert, ReadDefault, ReadInt2Fpu]>;
527527

528-
def MMX_PINSRWrm : MMXIi8<0xC4, MRMSrcMem,
528+
def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
529529
(outs VR64:$dst),
530530
(ins VR64:$src1, i16mem:$src2, i32u8imm:$src3),
531531
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",

‎llvm/lib/Target/X86/X86InstrSSE.td

Lines changed: 29 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -3989,7 +3989,7 @@ let Constraints = "$src1 = $dst" in {
39893989

39903990
let ExeDomain = SSEPackedInt in {
39913991
multiclass sse2_pinsrw<bit Is2Addr = 1> {
3992-
def rr : Ii8<0xC4, MRMSrcReg,
3992+
def rri : Ii8<0xC4, MRMSrcReg,
39933993
(outs VR128:$dst), (ins VR128:$src1,
39943994
GR32orGR64:$src2, u8imm:$src3),
39953995
!if(Is2Addr,
@@ -3998,7 +3998,7 @@ multiclass sse2_pinsrw<bit Is2Addr = 1> {
39983998
[(set VR128:$dst,
39993999
(X86pinsrw VR128:$src1, GR32orGR64:$src2, timm:$src3))]>,
40004000
Sched<[WriteVecInsert, ReadDefault, ReadInt2Fpu]>;
4001-
def rm : Ii8<0xC4, MRMSrcMem,
4001+
def rmi : Ii8<0xC4, MRMSrcMem,
40024002
(outs VR128:$dst), (ins VR128:$src1,
40034003
i16mem:$src2, u8imm:$src3),
40044004
!if(Is2Addr,
@@ -4012,13 +4012,13 @@ multiclass sse2_pinsrw<bit Is2Addr = 1> {
40124012

40134013
// Extract
40144014
let Predicates = [HasAVX, NoBWI] in
4015-
def VPEXTRWrr : Ii8<0xC5, MRMSrcReg,
4015+
def VPEXTRWrri : Ii8<0xC5, MRMSrcReg,
40164016
(outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
40174017
"vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
40184018
[(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
40194019
timm:$src2))]>,
40204020
TB, PD, VEX, WIG, Sched<[WriteVecExtract]>;
4021-
def PEXTRWrr : PDIi8<0xC5, MRMSrcReg,
4021+
def PEXTRWrri : PDIi8<0xC5, MRMSrcReg,
40224022
(outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
40234023
"pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
40244024
[(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
@@ -4036,16 +4036,16 @@ defm PINSRW : sse2_pinsrw, TB, PD;
40364036

40374037
// Always select FP16 instructions if available.
40384038
let Predicates = [UseSSE2], AddedComplexity = -10 in {
4039-
def : Pat<(f16 (load addr:$src)), (COPY_TO_REGCLASS (PINSRWrm (v8i16 (IMPLICIT_DEF)), addr:$src, 0), FR16)>;
4040-
def : Pat<(store f16:$src, addr:$dst), (MOV16mr addr:$dst, (EXTRACT_SUBREG (PEXTRWrr (v8i16 (COPY_TO_REGCLASS FR16:$src, VR128)), 0), sub_16bit))>;
4041-
def : Pat<(i16 (bitconvert f16:$src)), (EXTRACT_SUBREG (PEXTRWrr (v8i16 (COPY_TO_REGCLASS FR16:$src, VR128)), 0), sub_16bit)>;
4042-
def : Pat<(f16 (bitconvert i16:$src)), (COPY_TO_REGCLASS (PINSRWrr (v8i16 (IMPLICIT_DEF)), (INSERT_SUBREG (IMPLICIT_DEF), GR16:$src, sub_16bit), 0), FR16)>;
4039+
def : Pat<(f16 (load addr:$src)), (COPY_TO_REGCLASS (PINSRWrmi (v8i16 (IMPLICIT_DEF)), addr:$src, 0), FR16)>;
4040+
def : Pat<(store f16:$src, addr:$dst), (MOV16mr addr:$dst, (EXTRACT_SUBREG (PEXTRWrri (v8i16 (COPY_TO_REGCLASS FR16:$src, VR128)), 0), sub_16bit))>;
4041+
def : Pat<(i16 (bitconvert f16:$src)), (EXTRACT_SUBREG (PEXTRWrri (v8i16 (COPY_TO_REGCLASS FR16:$src, VR128)), 0), sub_16bit)>;
4042+
def : Pat<(f16 (bitconvert i16:$src)), (COPY_TO_REGCLASS (PINSRWrri (v8i16 (IMPLICIT_DEF)), (INSERT_SUBREG (IMPLICIT_DEF), GR16:$src, sub_16bit), 0), FR16)>;
40434043
}
40444044

40454045
let Predicates = [HasAVX, NoBWI] in {
4046-
def : Pat<(f16 (load addr:$src)), (COPY_TO_REGCLASS (VPINSRWrm (v8i16 (IMPLICIT_DEF)), addr:$src, 0), FR16)>;
4047-
def : Pat<(i16 (bitconvert f16:$src)), (EXTRACT_SUBREG (VPEXTRWrr (v8i16 (COPY_TO_REGCLASS FR16:$src, VR128)), 0), sub_16bit)>;
4048-
def : Pat<(f16 (bitconvert i16:$src)), (COPY_TO_REGCLASS (VPINSRWrr (v8i16 (IMPLICIT_DEF)), (INSERT_SUBREG (IMPLICIT_DEF), GR16:$src, sub_16bit), 0), FR16)>;
4046+
def : Pat<(f16 (load addr:$src)), (COPY_TO_REGCLASS (VPINSRWrmi (v8i16 (IMPLICIT_DEF)), addr:$src, 0), FR16)>;
4047+
def : Pat<(i16 (bitconvert f16:$src)), (EXTRACT_SUBREG (VPEXTRWrri (v8i16 (COPY_TO_REGCLASS FR16:$src, VR128)), 0), sub_16bit)>;
4048+
def : Pat<(f16 (bitconvert i16:$src)), (COPY_TO_REGCLASS (VPINSRWrri (v8i16 (IMPLICIT_DEF)), (INSERT_SUBREG (IMPLICIT_DEF), GR16:$src, sub_16bit), 0), FR16)>;
40494049
}
40504050

40514051
//===---------------------------------------------------------------------===//
@@ -5234,15 +5234,15 @@ let Predicates = [UseSSE41] in {
52345234

52355235
/// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
52365236
multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5237-
def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
5237+
def rri : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
52385238
(ins VR128:$src1, u8imm:$src2),
52395239
!strconcat(OpcodeStr,
52405240
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
52415241
[(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
52425242
timm:$src2))]>,
52435243
Sched<[WriteVecExtract]>;
52445244
let hasSideEffects = 0, mayStore = 1 in
5245-
def mr : SS4AIi8<opc, MRMDestMem, (outs),
5245+
def mri : SS4AIi8<opc, MRMDestMem, (outs),
52465246
(ins i8mem:$dst, VR128:$src1, u8imm:$src2),
52475247
!strconcat(OpcodeStr,
52485248
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
@@ -5259,14 +5259,14 @@ defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
52595259
/// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
52605260
multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
52615261
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
5262-
def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
5262+
def rri_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
52635263
(ins VR128:$src1, u8imm:$src2),
52645264
!strconcat(OpcodeStr,
52655265
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
52665266
Sched<[WriteVecExtract]>;
52675267

52685268
let hasSideEffects = 0, mayStore = 1 in
5269-
def mr : SS4AIi8<opc, MRMDestMem, (outs),
5269+
def mri : SS4AIi8<opc, MRMDestMem, (outs),
52705270
(ins i16mem:$dst, VR128:$src1, u8imm:$src2),
52715271
!strconcat(OpcodeStr,
52725272
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
@@ -5280,22 +5280,22 @@ let Predicates = [HasAVX, NoBWI] in
52805280
defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
52815281

52825282
let Predicates = [UseSSE41] in
5283-
def : Pat<(store f16:$src, addr:$dst), (PEXTRWmr addr:$dst, (v8i16 (COPY_TO_REGCLASS FR16:$src, VR128)), 0)>;
5283+
def : Pat<(store f16:$src, addr:$dst), (PEXTRWmri addr:$dst, (v8i16 (COPY_TO_REGCLASS FR16:$src, VR128)), 0)>;
52845284

52855285
let Predicates = [HasAVX, NoBWI] in
5286-
def : Pat<(store f16:$src, addr:$dst), (VPEXTRWmr addr:$dst, (v8i16 (COPY_TO_REGCLASS FR16:$src, VR128)), 0)>;
5286+
def : Pat<(store f16:$src, addr:$dst), (VPEXTRWmri addr:$dst, (v8i16 (COPY_TO_REGCLASS FR16:$src, VR128)), 0)>;
52875287

52885288

52895289
/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
52905290
multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5291-
def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5291+
def rri : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
52925292
(ins VR128:$src1, u8imm:$src2),
52935293
!strconcat(OpcodeStr,
52945294
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
52955295
[(set GR32:$dst,
52965296
(extractelt (v4i32 VR128:$src1), imm:$src2))]>,
52975297
Sched<[WriteVecExtract]>;
5298-
def mr : SS4AIi8<opc, MRMDestMem, (outs),
5298+
def mri : SS4AIi8<opc, MRMDestMem, (outs),
52995299
(ins i32mem:$dst, VR128:$src1, u8imm:$src2),
53005300
!strconcat(OpcodeStr,
53015301
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
@@ -5310,14 +5310,14 @@ defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
53105310

53115311
/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
53125312
multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5313-
def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5313+
def rri : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
53145314
(ins VR128:$src1, u8imm:$src2),
53155315
!strconcat(OpcodeStr,
53165316
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
53175317
[(set GR64:$dst,
53185318
(extractelt (v2i64 VR128:$src1), imm:$src2))]>,
53195319
Sched<[WriteVecExtract]>;
5320-
def mr : SS4AIi8<opc, MRMDestMem, (outs),
5320+
def mri : SS4AIi8<opc, MRMDestMem, (outs),
53215321
(ins i64mem:$dst, VR128:$src1, u8imm:$src2),
53225322
!strconcat(OpcodeStr,
53235323
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
@@ -5359,7 +5359,7 @@ let ExeDomain = SSEPackedSingle in {
53595359
//===----------------------------------------------------------------------===//
53605360

53615361
multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5362-
def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5362+
def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
53635363
(ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
53645364
!if(Is2Addr,
53655365
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
@@ -5368,7 +5368,7 @@ multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
53685368
[(set VR128:$dst,
53695369
(X86pinsrb VR128:$src1, GR32orGR64:$src2, timm:$src3))]>,
53705370
Sched<[WriteVecInsert, ReadDefault, ReadInt2Fpu]>;
5371-
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5371+
def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
53725372
(ins VR128:$src1, i8mem:$src2, u8imm:$src3),
53735373
!if(Is2Addr,
53745374
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
@@ -5382,15 +5382,15 @@ multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
53825382
let Predicates = [HasAVX, NoBWI] in {
53835383
defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX, VVVV, WIG;
53845384
def : Pat<(X86pinsrb VR128:$src1, (i32 (anyext (i8 GR8:$src2))), timm:$src3),
5385-
(VPINSRBrr VR128:$src1, (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
5386-
GR8:$src2, sub_8bit), timm:$src3)>;
5385+
(VPINSRBrri VR128:$src1, (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
5386+
GR8:$src2, sub_8bit), timm:$src3)>;
53875387
}
53885388

53895389
let Constraints = "$src1 = $dst" in
53905390
defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
53915391

53925392
multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5393-
def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5393+
def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
53945394
(ins VR128:$src1, GR32:$src2, u8imm:$src3),
53955395
!if(Is2Addr,
53965396
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
@@ -5399,7 +5399,7 @@ multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
53995399
[(set VR128:$dst,
54005400
(v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
54015401
Sched<[WriteVecInsert, ReadDefault, ReadInt2Fpu]>;
5402-
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5402+
def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
54035403
(ins VR128:$src1, i32mem:$src2, u8imm:$src3),
54045404
!if(Is2Addr,
54055405
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
@@ -5416,7 +5416,7 @@ let Constraints = "$src1 = $dst" in
54165416
defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
54175417

54185418
multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5419-
def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5419+
def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
54205420
(ins VR128:$src1, GR64:$src2, u8imm:$src3),
54215421
!if(Is2Addr,
54225422
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
@@ -5425,7 +5425,7 @@ multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
54255425
[(set VR128:$dst,
54265426
(v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
54275427
Sched<[WriteVecInsert, ReadDefault, ReadInt2Fpu]>;
5428-
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5428+
def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
54295429
(ins VR128:$src1, i64mem:$src2, u8imm:$src3),
54305430
!if(Is2Addr,
54315431
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),

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