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[AMDGPU][True16][MC] update true16 flag on vinterp test (#115356)
A non-funcitonal change. update true16 flag on vinterp dasm test
1 parent 3deee23 commit 1fef4ad

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‎llvm/test/MC/Disassembler/AMDGPU/vinterp-fake16.txt renamed to ‎llvm/test/MC/Disassembler/AMDGPU/vinterp.txt

Lines changed: 88 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -1,252 +1,255 @@
1-
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefix=CHECK %s
2-
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefix=CHECK %s
1+
# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK %s
3+
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK %s
4+
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK %s
5+
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK %s
36

4-
# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:0{{$}}
57
0x00,0x00,0x00,0xcd,0x01,0x05,0x0e,0x04
8+
# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:0
69

710
# Check that unused bits in the encoding are ignored.
8-
# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:0{{$}}
911
0x00,0x00,0x80,0xcd,0x01,0x05,0x0e,0x1c
12+
# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:0
1013

11-
# CHECK: v_interp_p10_f32 v1, v10, v20, v30 wait_exp:0{{$}}
1214
0x01,0x00,0x00,0xcd,0x0a,0x29,0x7a,0x04
15+
# CHECK: v_interp_p10_f32 v1, v10, v20, v30 wait_exp:0
1316

14-
# CHECK: v_interp_p10_f32 v2, v11, v21, v31 wait_exp:0{{$}}
1517
0x02,0x00,0x00,0xcd,0x0b,0x2b,0x7e,0x04
18+
# CHECK: v_interp_p10_f32 v2, v11, v21, v31 wait_exp:0
1619

17-
# CHECK: v_interp_p10_f32 v3, v12, v22, v32 wait_exp:0{{$}}
1820
0x03,0x00,0x00,0xcd,0x0c,0x2d,0x82,0x04
21+
# CHECK: v_interp_p10_f32 v3, v12, v22, v32 wait_exp:0
1922

20-
# CHECK: v_interp_p10_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}}
2123
0x00,0x80,0x00,0xcd,0x01,0x05,0x0e,0x04
24+
# CHECK: v_interp_p10_f32 v0, v1, v2, v3 clamp wait_exp:0
2225

23-
# CHECK: v_interp_p10_f32 v0, -v1, v2, v3 wait_exp:0{{$}}
2426
0x00,0x00,0x00,0xcd,0x01,0x05,0x0e,0x24
27+
# CHECK: v_interp_p10_f32 v0, -v1, v2, v3 wait_exp:0
2528

26-
# CHECK: v_interp_p10_f32 v0, v1, -v2, v3 wait_exp:0{{$}}
2729
0x00,0x00,0x00,0xcd,0x01,0x05,0x0e,0x44
30+
# CHECK: v_interp_p10_f32 v0, v1, -v2, v3 wait_exp:0
2831

29-
# CHECK: v_interp_p10_f32 v0, v1, v2, -v3 wait_exp:0{{$}}
3032
0x00,0x00,0x00,0xcd,0x01,0x05,0x0e,0x84
33+
# CHECK: v_interp_p10_f32 v0, v1, v2, -v3 wait_exp:0
3134

32-
# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:1{{$}}
3335
0x00,0x01,0x00,0xcd,0x01,0x05,0x0e,0x04
36+
# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:1
3437

35-
# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:7{{$}}
3638
0x00,0x07,0x00,0xcd,0x01,0x05,0x0e,0x04
39+
# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:7
3740

38-
# CHECK: v_interp_p10_f32 v0, v1, v2, v3 clamp wait_exp:7{{$}}
3941
0x00,0x87,0x00,0xcd,0x01,0x05,0x0e,0x04
42+
# CHECK: v_interp_p10_f32 v0, v1, v2, v3 clamp wait_exp:7
4043

41-
# CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:0{{$}}
4244
0x00,0x00,0x01,0xcd,0x01,0x05,0x0e,0x04
45+
# CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:0
4346

44-
# CHECK: v_interp_p2_f32 v1, v10, v20, v30 wait_exp:0{{$}}
4547
0x01,0x00,0x01,0xcd,0x0a,0x29,0x7a,0x04
48+
# CHECK: v_interp_p2_f32 v1, v10, v20, v30 wait_exp:0
4649

47-
# CHECK: v_interp_p2_f32 v2, v11, v21, v31 wait_exp:0{{$}}
4850
0x02,0x00,0x01,0xcd,0x0b,0x2b,0x7e,0x04
51+
# CHECK: v_interp_p2_f32 v2, v11, v21, v31 wait_exp:0
4952

50-
# CHECK: v_interp_p2_f32 v3, v12, v22, v32 wait_exp:0{{$}}
5153
0x03,0x00,0x01,0xcd,0x0c,0x2d,0x82,0x04
54+
# CHECK: v_interp_p2_f32 v3, v12, v22, v32 wait_exp:0
5255

53-
# CHECK: v_interp_p2_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}}
5456
0x00,0x80,0x01,0xcd,0x01,0x05,0x0e,0x04
57+
# CHECK: v_interp_p2_f32 v0, v1, v2, v3 clamp wait_exp:0
5558

56-
# CHECK: v_interp_p2_f32 v0, -v1, v2, v3 wait_exp:0{{$}}
5759
0x00,0x00,0x01,0xcd,0x01,0x05,0x0e,0x24
60+
# CHECK: v_interp_p2_f32 v0, -v1, v2, v3 wait_exp:0
5861

59-
# CHECK: v_interp_p2_f32 v0, v1, -v2, v3 wait_exp:0{{$}}
6062
0x00,0x00,0x01,0xcd,0x01,0x05,0x0e,0x44
63+
# CHECK: v_interp_p2_f32 v0, v1, -v2, v3 wait_exp:0
6164

62-
# CHECK: v_interp_p2_f32 v0, v1, v2, -v3 wait_exp:0{{$}}
6365
0x00,0x00,0x01,0xcd,0x01,0x05,0x0e,0x84
66+
# CHECK: v_interp_p2_f32 v0, v1, v2, -v3 wait_exp:0
6467

65-
# CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:1{{$}}
6668
0x00,0x01,0x01,0xcd,0x01,0x05,0x0e,0x04
69+
# CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:1
6770

68-
# CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:7{{$}}
6971
0x00,0x07,0x01,0xcd,0x01,0x05,0x0e,0x04
72+
# CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:7
7073

71-
# CHECK: v_interp_p2_f32 v0, v1, v2, v3 clamp wait_exp:7{{$}}
7274
0x00,0x87,0x01,0xcd,0x01,0x05,0x0e,0x04
75+
# CHECK: v_interp_p2_f32 v0, v1, v2, v3 clamp wait_exp:7
7376

74-
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:0{{$}}
7577
0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x04
78+
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:0
7679

77-
# CHECK: v_interp_p10_f16_f32 v0, -v1, v2, v3 wait_exp:0{{$}}
7880
0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x24
81+
# CHECK: v_interp_p10_f16_f32 v0, -v1, v2, v3 wait_exp:0
7982

80-
# CHECK: v_interp_p10_f16_f32 v0, v1, -v2, v3 wait_exp:0{{$}}
8183
0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x44
84+
# CHECK: v_interp_p10_f16_f32 v0, v1, -v2, v3 wait_exp:0
8285

83-
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, -v3 wait_exp:0{{$}}
8486
0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x84
87+
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, -v3 wait_exp:0
8588

86-
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}}
8789
0x00,0x80,0x02,0xcd,0x01,0x05,0x0e,0x04
90+
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 clamp wait_exp:0
8891

89-
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:1{{$}}
9092
0x00,0x01,0x02,0xcd,0x01,0x05,0x0e,0x04
93+
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:1
9194

92-
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:7{{$}}
9395
0x00,0x07,0x02,0xcd,0x01,0x05,0x0e,0x04
96+
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:7
9497

95-
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0{{$}}
9698
0x00,0x08,0x02,0xcd,0x01,0x05,0x0e,0x04
99+
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0
97100

98-
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0{{$}}
99101
0x00,0x10,0x02,0xcd,0x01,0x05,0x0e,0x04
102+
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0
100103

101-
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0{{$}}
102104
0x00,0x20,0x02,0xcd,0x01,0x05,0x0e,0x04
105+
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0
103106

104-
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0{{$}}
105107
0x00,0x40,0x02,0xcd,0x01,0x05,0x0e,0x04
108+
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0
106109

107-
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0{{$}}
108110
0x00,0x78,0x02,0xcd,0x01,0x05,0x0e,0x04
111+
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0
109112

110-
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5{{$}}
111113
0x00,0x4d,0x02,0xcd,0x01,0x05,0x0e,0x04
114+
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5
112115

113-
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
114116
0x00,0xcd,0x02,0xcd,0x01,0x05,0x0e,0x04
117+
# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5
115118

116-
# CHECK: v_interp_p10_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
117119
0x00,0xcd,0x02,0xcd,0x01,0x05,0x0e,0xe4
120+
# CHECK: v_interp_p10_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5
118121

119-
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:0{{$}}
120122
0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x04
123+
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:0
121124

122-
# CHECK: v_interp_p2_f16_f32 v0, -v1, v2, v3 wait_exp:0{{$}}
123125
0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x24
126+
# CHECK: v_interp_p2_f16_f32 v0, -v1, v2, v3 wait_exp:0
124127

125-
# CHECK: v_interp_p2_f16_f32 v0, v1, -v2, v3 wait_exp:0{{$}}
126128
0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x44
129+
# CHECK: v_interp_p2_f16_f32 v0, v1, -v2, v3 wait_exp:0
127130

128-
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, -v3 wait_exp:0{{$}}
129131
0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x84
132+
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, -v3 wait_exp:0
130133

131-
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}}
132134
0x00,0x80,0x03,0xcd,0x01,0x05,0x0e,0x04
135+
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 clamp wait_exp:0
133136

134-
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:1{{$}}
135137
0x00,0x01,0x03,0xcd,0x01,0x05,0x0e,0x04
138+
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:1
136139

137-
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:7{{$}}
138140
0x00,0x07,0x03,0xcd,0x01,0x05,0x0e,0x04
141+
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:7
139142

140-
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0{{$}}
141143
0x00,0x08,0x03,0xcd,0x01,0x05,0x0e,0x04
144+
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0
142145

143-
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0{{$}}
144146
0x00,0x10,0x03,0xcd,0x01,0x05,0x0e,0x04
147+
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0
145148

146-
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0{{$}}
147149
0x00,0x20,0x03,0xcd,0x01,0x05,0x0e,0x04
150+
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0
148151

149-
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0{{$}}
150152
0x00,0x40,0x03,0xcd,0x01,0x05,0x0e,0x04
153+
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0
151154

152-
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0{{$}}
153155
0x00,0x78,0x03,0xcd,0x01,0x05,0x0e,0x04
156+
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0
154157

155-
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5{{$}}
156158
0x00,0x4d,0x03,0xcd,0x01,0x05,0x0e,0x04
159+
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5
157160

158-
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
159161
0x00,0xcd,0x03,0xcd,0x01,0x05,0x0e,0x04
162+
# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5
160163

161-
# CHECK: v_interp_p2_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
162164
0x00,0xcd,0x03,0xcd,0x01,0x05,0x0e,0xe4
165+
# CHECK: v_interp_p2_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5
163166

164-
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0{{$}}
165167
0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x04
168+
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0
166169

167-
# CHECK: v_interp_p10_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0{{$}}
168170
0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x24
171+
# CHECK: v_interp_p10_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0
169172

170-
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, -v2, v3 wait_exp:0{{$}}
171173
0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x44
174+
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, -v2, v3 wait_exp:0
172175

173-
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, -v3 wait_exp:0{{$}}
174176
0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x84
177+
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, -v3 wait_exp:0
175178

176-
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}}
177179
0x00,0x80,0x04,0xcd,0x01,0x05,0x0e,0x04
180+
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 clamp wait_exp:0
178181

179-
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:1{{$}}
180182
0x00,0x01,0x04,0xcd,0x01,0x05,0x0e,0x04
183+
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:1
181184

182-
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:7{{$}}
183185
0x00,0x07,0x04,0xcd,0x01,0x05,0x0e,0x04
186+
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:7
184187

185-
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0{{$}}
186188
0x00,0x08,0x04,0xcd,0x01,0x05,0x0e,0x04
189+
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0
187190

188-
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0{{$}}
189191
0x00,0x10,0x04,0xcd,0x01,0x05,0x0e,0x04
192+
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0
190193

191-
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0{{$}}
192194
0x00,0x20,0x04,0xcd,0x01,0x05,0x0e,0x04
195+
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0
193196

194-
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0{{$}}
195197
0x00,0x40,0x04,0xcd,0x01,0x05,0x0e,0x04
198+
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0
196199

197-
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0{{$}}
198200
0x00,0x78,0x04,0xcd,0x01,0x05,0x0e,0x04
201+
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0
199202

200-
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5{{$}}
201203
0x00,0x4d,0x04,0xcd,0x01,0x05,0x0e,0x04
204+
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5
202205

203-
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
204206
0x00,0xcd,0x04,0xcd,0x01,0x05,0x0e,0x04
207+
# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5
205208

206-
# CHECK: v_interp_p10_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
207209
0x00,0xcd,0x04,0xcd,0x01,0x05,0x0e,0xe4
210+
# CHECK: v_interp_p10_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5
208211

209-
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0{{$}}
210212
0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x04
213+
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0
211214

212-
# CHECK: v_interp_p2_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0{{$}}
213215
0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x24
216+
# CHECK: v_interp_p2_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0
214217

215-
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, -v2, v3 wait_exp:0{{$}}
216218
0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x44
219+
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, -v2, v3 wait_exp:0
217220

218-
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, -v3 wait_exp:0{{$}}
219221
0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x84
222+
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, -v3 wait_exp:0
220223

221-
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}}
222224
0x00,0x80,0x05,0xcd,0x01,0x05,0x0e,0x04
225+
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 clamp wait_exp:0
223226

224-
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:1{{$}}
225227
0x00,0x01,0x05,0xcd,0x01,0x05,0x0e,0x04
228+
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:1
226229

227-
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:7{{$}}
228230
0x00,0x07,0x05,0xcd,0x01,0x05,0x0e,0x04
231+
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:7
229232

230-
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0{{$}}
231233
0x00,0x08,0x05,0xcd,0x01,0x05,0x0e,0x04
234+
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0
232235

233-
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0{{$}}
234236
0x00,0x10,0x05,0xcd,0x01,0x05,0x0e,0x04
237+
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0
235238

236-
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0{{$}}
237239
0x00,0x20,0x05,0xcd,0x01,0x05,0x0e,0x04
240+
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0
238241

239-
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0{{$}}
240242
0x00,0x40,0x05,0xcd,0x01,0x05,0x0e,0x04
243+
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0
241244

242-
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0{{$}}
243245
0x00,0x78,0x05,0xcd,0x01,0x05,0x0e,0x04
246+
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0
244247

245-
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5{{$}}
246248
0x00,0x4d,0x05,0xcd,0x01,0x05,0x0e,0x04
249+
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5
247250

248-
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
249251
0x00,0xcd,0x05,0xcd,0x01,0x05,0x0e,0x04
252+
# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5
250253

251-
# CHECK: v_interp_p2_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
252254
0x00,0xcd,0x05,0xcd,0x01,0x05,0x0e,0xe4
255+
# CHECK: v_interp_p2_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5

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