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Merged
merged 1 commit into from
Nov 7, 2024
Merged

[AMDGPU][True16][MC] update true16 flag on vinterp test #115356

merged 1 commit into from
Nov 7, 2024

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@broxigarchen broxigarchen commented Nov 7, 2024 •
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A non-funcitonal change.

update true16 flag on vinterp dasm test

@broxigarchen broxigarchen marked this pull request as ready for review November 7, 2024 18:29
@broxigarchen broxigarchen requested a review from Sisyph November 7, 2024 18:29
@llvmbot llvmbot added backend:AMDGPU mc Machine (object) code labels Nov 7, 2024
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llvmbot commented Nov 7, 2024 •
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@llvm/pr-subscribers-backend-amdgpu

@llvm/pr-subscribers-mc

Author: Brox Chen (broxigarchen)

Changes

update true16 flag on vinterp dasm test

Full diff: https://github.com/llvm/llvm-project/pull/115356.diff

1 Files Affected:

  • (renamed) llvm/test/MC/Disassembler/AMDGPU/vinterp.txt (+88-85)
diff --git a/llvm/test/MC/Disassembler/AMDGPU/vinterp-fake16.txt b/llvm/test/MC/Disassembler/AMDGPU/vinterp.txt
similarity index 60%
rename from llvm/test/MC/Disassembler/AMDGPU/vinterp-fake16.txt
rename to llvm/test/MC/Disassembler/AMDGPU/vinterp.txt
index 239f1d8b3058da..0e19f39764e7f8 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/vinterp-fake16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/vinterp.txt
@@ -1,252 +1,255 @@
-# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefix=CHECK %s
-# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefix=CHECK %s
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK %s
 
-# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x00,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:0
 
 # Check that unused bits in the encoding are ignored.
-# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x80,0xcd,0x01,0x05,0x0e,0x1c
+# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:0
 
-# CHECK: v_interp_p10_f32 v1, v10, v20, v30 wait_exp:0{{$}}
 0x01,0x00,0x00,0xcd,0x0a,0x29,0x7a,0x04
+# CHECK: v_interp_p10_f32 v1, v10, v20, v30 wait_exp:0
 
-# CHECK: v_interp_p10_f32 v2, v11, v21, v31 wait_exp:0{{$}}
 0x02,0x00,0x00,0xcd,0x0b,0x2b,0x7e,0x04
+# CHECK: v_interp_p10_f32 v2, v11, v21, v31 wait_exp:0
 
-# CHECK: v_interp_p10_f32 v3, v12, v22, v32 wait_exp:0{{$}}
 0x03,0x00,0x00,0xcd,0x0c,0x2d,0x82,0x04
+# CHECK: v_interp_p10_f32 v3, v12, v22, v32 wait_exp:0
 
-# CHECK: v_interp_p10_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}}
 0x00,0x80,0x00,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f32 v0, v1, v2, v3 clamp wait_exp:0
 
-# CHECK: v_interp_p10_f32 v0, -v1, v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x00,0xcd,0x01,0x05,0x0e,0x24
+# CHECK: v_interp_p10_f32 v0, -v1, v2, v3 wait_exp:0
 
-# CHECK: v_interp_p10_f32 v0, v1, -v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x00,0xcd,0x01,0x05,0x0e,0x44
+# CHECK: v_interp_p10_f32 v0, v1, -v2, v3 wait_exp:0
 
-# CHECK: v_interp_p10_f32 v0, v1, v2, -v3 wait_exp:0{{$}}
 0x00,0x00,0x00,0xcd,0x01,0x05,0x0e,0x84
+# CHECK: v_interp_p10_f32 v0, v1, v2, -v3 wait_exp:0
 
-# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:1{{$}}
 0x00,0x01,0x00,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:1
 
-# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:7{{$}}
 0x00,0x07,0x00,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:7
 
-# CHECK: v_interp_p10_f32 v0, v1, v2, v3 clamp wait_exp:7{{$}}
 0x00,0x87,0x00,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f32 v0, v1, v2, v3 clamp wait_exp:7
 
-# CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x01,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:0
 
-# CHECK: v_interp_p2_f32 v1, v10, v20, v30 wait_exp:0{{$}}
 0x01,0x00,0x01,0xcd,0x0a,0x29,0x7a,0x04
+# CHECK: v_interp_p2_f32 v1, v10, v20, v30 wait_exp:0
 
-# CHECK: v_interp_p2_f32 v2, v11, v21, v31 wait_exp:0{{$}}
 0x02,0x00,0x01,0xcd,0x0b,0x2b,0x7e,0x04
+# CHECK: v_interp_p2_f32 v2, v11, v21, v31 wait_exp:0
 
-# CHECK: v_interp_p2_f32 v3, v12, v22, v32 wait_exp:0{{$}}
 0x03,0x00,0x01,0xcd,0x0c,0x2d,0x82,0x04
+# CHECK: v_interp_p2_f32 v3, v12, v22, v32 wait_exp:0
 
-# CHECK: v_interp_p2_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}}
 0x00,0x80,0x01,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f32 v0, v1, v2, v3 clamp wait_exp:0
 
-# CHECK: v_interp_p2_f32 v0, -v1, v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x01,0xcd,0x01,0x05,0x0e,0x24
+# CHECK: v_interp_p2_f32 v0, -v1, v2, v3 wait_exp:0
 
-# CHECK: v_interp_p2_f32 v0, v1, -v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x01,0xcd,0x01,0x05,0x0e,0x44
+# CHECK: v_interp_p2_f32 v0, v1, -v2, v3 wait_exp:0
 
-# CHECK: v_interp_p2_f32 v0, v1, v2, -v3 wait_exp:0{{$}}
 0x00,0x00,0x01,0xcd,0x01,0x05,0x0e,0x84
+# CHECK: v_interp_p2_f32 v0, v1, v2, -v3 wait_exp:0
 
-# CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:1{{$}}
 0x00,0x01,0x01,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:1
 
-# CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:7{{$}}
 0x00,0x07,0x01,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:7
 
-# CHECK: v_interp_p2_f32 v0, v1, v2, v3 clamp wait_exp:7{{$}}
 0x00,0x87,0x01,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f32 v0, v1, v2, v3 clamp wait_exp:7
 
-# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:0
 
-# CHECK: v_interp_p10_f16_f32 v0, -v1, v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x24
+# CHECK: v_interp_p10_f16_f32 v0, -v1, v2, v3 wait_exp:0
 
-# CHECK: v_interp_p10_f16_f32 v0, v1, -v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x44
+# CHECK: v_interp_p10_f16_f32 v0, v1, -v2, v3 wait_exp:0
 
-# CHECK: v_interp_p10_f16_f32 v0, v1, v2, -v3 wait_exp:0{{$}}
 0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x84
+# CHECK: v_interp_p10_f16_f32 v0, v1, v2, -v3 wait_exp:0
 
-# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}}
 0x00,0x80,0x02,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 clamp wait_exp:0
 
-# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:1{{$}}
 0x00,0x01,0x02,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:1
 
-# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:7{{$}}
 0x00,0x07,0x02,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:7
 
-# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0{{$}}
 0x00,0x08,0x02,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0
 
-# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0{{$}}
 0x00,0x10,0x02,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0
 
-# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0{{$}}
 0x00,0x20,0x02,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0
 
-# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0{{$}}
 0x00,0x40,0x02,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0
 
-# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0{{$}}
 0x00,0x78,0x02,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0
 
-# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5{{$}}
 0x00,0x4d,0x02,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5
 
-# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
 0x00,0xcd,0x02,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5
 
-# CHECK: v_interp_p10_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
 0x00,0xcd,0x02,0xcd,0x01,0x05,0x0e,0xe4
+# CHECK: v_interp_p10_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5
 
-# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:0
 
-# CHECK: v_interp_p2_f16_f32 v0, -v1, v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x24
+# CHECK: v_interp_p2_f16_f32 v0, -v1, v2, v3 wait_exp:0
 
-# CHECK: v_interp_p2_f16_f32 v0, v1, -v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x44
+# CHECK: v_interp_p2_f16_f32 v0, v1, -v2, v3 wait_exp:0
 
-# CHECK: v_interp_p2_f16_f32 v0, v1, v2, -v3 wait_exp:0{{$}}
 0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x84
+# CHECK: v_interp_p2_f16_f32 v0, v1, v2, -v3 wait_exp:0
 
-# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}}
 0x00,0x80,0x03,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 clamp wait_exp:0
 
-# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:1{{$}}
 0x00,0x01,0x03,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:1
 
-# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:7{{$}}
 0x00,0x07,0x03,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:7
 
-# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0{{$}}
 0x00,0x08,0x03,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0
 
-# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0{{$}}
 0x00,0x10,0x03,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0
 
-# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0{{$}}
 0x00,0x20,0x03,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0
 
-# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0{{$}}
 0x00,0x40,0x03,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0
 
-# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0{{$}}
 0x00,0x78,0x03,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0
 
-# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5{{$}}
 0x00,0x4d,0x03,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5
 
-# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
 0x00,0xcd,0x03,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5
 
-# CHECK: v_interp_p2_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
 0x00,0xcd,0x03,0xcd,0x01,0x05,0x0e,0xe4
+# CHECK: v_interp_p2_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x24
+# CHECK: v_interp_p10_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, -v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x44
+# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, -v2, v3 wait_exp:0
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, -v3 wait_exp:0{{$}}
 0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x84
+# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, -v3 wait_exp:0
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}}
 0x00,0x80,0x04,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 clamp wait_exp:0
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:1{{$}}
 0x00,0x01,0x04,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:1
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:7{{$}}
 0x00,0x07,0x04,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:7
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0{{$}}
 0x00,0x08,0x04,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0{{$}}
 0x00,0x10,0x04,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0{{$}}
 0x00,0x20,0x04,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0{{$}}
 0x00,0x40,0x04,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0{{$}}
 0x00,0x78,0x04,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5{{$}}
 0x00,0x4d,0x04,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
 0x00,0xcd,0x04,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5
 
-# CHECK: v_interp_p10_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
 0x00,0xcd,0x04,0xcd,0x01,0x05,0x0e,0xe4
+# CHECK: v_interp_p10_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x24
+# CHECK: v_interp_p2_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, -v2, v3 wait_exp:0{{$}}
 0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x44
+# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, -v2, v3 wait_exp:0
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, -v3 wait_exp:0{{$}}
 0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x84
+# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, -v3 wait_exp:0
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}}
 0x00,0x80,0x05,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 clamp wait_exp:0
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:1{{$}}
 0x00,0x01,0x05,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:1
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:7{{$}}
 0x00,0x07,0x05,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:7
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0{{$}}
 0x00,0x08,0x05,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0{{$}}
 0x00,0x10,0x05,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0{{$}}
 0x00,0x20,0x05,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0{{$}}
 0x00,0x40,0x05,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0{{$}}
 0x00,0x78,0x05,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5{{$}}
 0x00,0x4d,0x05,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
 0x00,0xcd,0x05,0xcd,0x01,0x05,0x0e,0x04
+# CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5
 
-# CHECK: v_interp_p2_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}}
 0x00,0xcd,0x05,0xcd,0x01,0x05,0x0e,0xe4
+# CHECK: v_interp_p2_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5

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The windows failure seems unrelated with this patch

@broxigarchen broxigarchen merged commit 1fef4ad into llvm:main Nov 7, 2024
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kosarev
kosarev reviewed Nov 12, 2024
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llvm/test/MC/Disassembler/AMDGPU/vinterp.txt
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefix=CHECK %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefix=CHECK %s
# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK %s
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@broxigarchen Why don't these tests do -show-encoding? We do seem to have encodings checked downstream.

Groverkss pushed a commit to iree-org/llvm-project that referenced this pull request Nov 15, 2024
@broxigarchen @Groverkss
[AMDGPU][True16][MC] update true16 flag on vinterp test (llvm#115356)
ce34e4a 
A non-funcitonal change.

update true16 flag on vinterp dasm test
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@kosarev kosarev kosarev left review comments

@arsenm arsenm arsenm approved these changes

@Sisyph Sisyph Sisyph approved these changes

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@broxigarchen @llvmbot @arsenm @kosarev @Sisyph