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Keep a more canonical form by copying masks from a virtual register first
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llvm/lib/Target/RISCV/RISCVFoldMasks.cpp

Lines changed: 13 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -79,16 +79,13 @@ INITIALIZE_PASS(RISCVFoldMasks, DEBUG_TYPE, "RISC-V Fold Masks", false, false)
7979
bool RISCVFoldMasks::isAllOnesMask(MachineInstr *MaskDef) {
8080
if (!MaskDef)
8181
return false;
82-
if (MaskDef->isCopy()) {
83-
assert(MaskDef->getOperand(0).getReg() == RISCV::V0);
84-
Register SrcReg =
85-
TRI->lookThruCopyLike(MaskDef->getOperand(1).getReg(), MRI);
86-
if (!SrcReg.isVirtual())
87-
return false;
88-
MaskDef = MRI->getVRegDef(SrcReg);
89-
if (!MaskDef)
90-
return false;
91-
}
82+
assert(MaskDef->isCopy() && MaskDef->getOperand(0).getReg() == RISCV::V0);
83+
Register SrcReg = TRI->lookThruCopyLike(MaskDef->getOperand(1).getReg(), MRI);
84+
if (!SrcReg.isVirtual())
85+
return false;
86+
MaskDef = MRI->getVRegDef(SrcReg);
87+
if (!MaskDef)
88+
return false;
9289

9390
// TODO: Check that the VMSET is the expected bitwidth? The pseudo has
9491
// undefined behaviour if it's the wrong bitwidth, so we could choose to
@@ -365,10 +362,14 @@ bool RISCVFoldMasks::foldVMergeIntoOps(MachineInstr &MI,
365362
// mask just before True.
366363
unsigned VMSetOpc =
367364
getVMSetForLMul(RISCVII::getLMul(MI.getDesc().TSFlags));
368-
BuildMI(*MI.getParent(), TrueMI, MI.getDebugLoc(), TII->get(VMSetOpc))
369-
.addDef(RISCV::V0)
365+
Register Dest = MRI->createVirtualRegister(&RISCV::VRRegClass);
366+
BuildMI(*MI.getParent(), TrueMI, MI.getDebugLoc(), TII->get(VMSetOpc),
367+
Dest)
370368
.add(VL)
371369
.add(TrueMI.getOperand(RISCVII::getSEWOpNum(TrueMCID)));
370+
BuildMI(*MI.getParent(), TrueMI, MI.getDebugLoc(), TII->get(RISCV::COPY),
371+
RISCV::V0)
372+
.addReg(Dest);
372373
}
373374

374375
TrueMI.setDesc(MaskedMCID);

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