@@ -79,16 +79,13 @@ INITIALIZE_PASS(RISCVFoldMasks, DEBUG_TYPE, "RISC-V Fold Masks", false, false)
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bool RISCVFoldMasks::isAllOnesMask(MachineInstr *MaskDef) {
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if (!MaskDef)
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return false ;
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- if (MaskDef->isCopy ()) {
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- assert (MaskDef->getOperand (0 ).getReg () == RISCV::V0);
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- Register SrcReg =
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- TRI->lookThruCopyLike (MaskDef->getOperand (1 ).getReg (), MRI);
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- if (!SrcReg.isVirtual ())
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- return false ;
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- MaskDef = MRI->getVRegDef (SrcReg);
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- if (!MaskDef)
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- return false ;
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- }
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+ assert (MaskDef->isCopy () && MaskDef->getOperand (0 ).getReg () == RISCV::V0);
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+ Register SrcReg = TRI->lookThruCopyLike (MaskDef->getOperand (1 ).getReg (), MRI);
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+ if (!SrcReg.isVirtual ())
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+ return false ;
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+ MaskDef = MRI->getVRegDef (SrcReg);
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+ if (!MaskDef)
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+ return false ;
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// TODO: Check that the VMSET is the expected bitwidth? The pseudo has
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// undefined behaviour if it's the wrong bitwidth, so we could choose to
@@ -365,10 +362,14 @@ bool RISCVFoldMasks::foldVMergeIntoOps(MachineInstr &MI,
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// mask just before True.
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unsigned VMSetOpc =
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getVMSetForLMul (RISCVII::getLMul (MI.getDesc ().TSFlags ));
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- BuildMI (*MI.getParent (), TrueMI, MI.getDebugLoc (), TII->get (VMSetOpc))
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- .addDef (RISCV::V0)
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+ Register Dest = MRI->createVirtualRegister (&RISCV::VRRegClass);
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+ BuildMI (*MI.getParent (), TrueMI, MI.getDebugLoc (), TII->get (VMSetOpc),
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+ Dest)
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.add (VL)
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.add (TrueMI.getOperand (RISCVII::getSEWOpNum (TrueMCID)));
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+ BuildMI (*MI.getParent (), TrueMI, MI.getDebugLoc (), TII->get (RISCV::COPY),
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+ RISCV::V0)
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+ .addReg (Dest);
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}
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TrueMI.setDesc (MaskedMCID);
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