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2 files changed

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‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 63 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -9116,67 +9116,67 @@ bool SIInstrInfo::isAsmOnlyOpcode(int MCOp) const {
91169116
}
91179117

91189118
bool SIInstrInfo::isRenamedInGFX9(int Opcode) const {
9119-
switch(Opcode) {
9120-
case AMDGPU::V_ADDC_U32_dpp:
9121-
case AMDGPU::V_ADDC_U32_e32:
9122-
case AMDGPU::V_ADDC_U32_e64:
9123-
case AMDGPU::V_ADDC_U32_e64_dpp:
9124-
case AMDGPU::V_ADDC_U32_sdwa:
9125-
//
9126-
case AMDGPU::V_ADD_CO_U32_dpp:
9127-
case AMDGPU::V_ADD_CO_U32_e32:
9128-
case AMDGPU::V_ADD_CO_U32_e64:
9129-
case AMDGPU::V_ADD_CO_U32_e64_dpp:
9130-
case AMDGPU::V_ADD_CO_U32_sdwa:
9131-
//
9132-
case AMDGPU::V_ADD_U32_dpp:
9133-
case AMDGPU::V_ADD_U32_e32:
9134-
case AMDGPU::V_ADD_U32_e64:
9135-
case AMDGPU::V_ADD_U32_e64_dpp:
9136-
case AMDGPU::V_ADD_U32_sdwa:
9137-
//
9138-
case AMDGPU::V_DIV_FIXUP_F16_gfx9_e64:
9139-
case AMDGPU::V_FMA_F16_gfx9_e64:
9140-
case AMDGPU::V_INTERP_P2_F16:
9141-
case AMDGPU::V_MAD_F16_e64:
9142-
case AMDGPU::V_MAD_U16_e64:
9143-
case AMDGPU::V_MAD_I16_e64:
9144-
//
9145-
case AMDGPU::V_SUBBREV_U32_dpp:
9146-
case AMDGPU::V_SUBBREV_U32_e32:
9147-
case AMDGPU::V_SUBBREV_U32_e64:
9148-
case AMDGPU::V_SUBBREV_U32_e64_dpp:
9149-
case AMDGPU::V_SUBBREV_U32_sdwa:
9150-
//
9151-
case AMDGPU::V_SUBB_U32_dpp:
9152-
case AMDGPU::V_SUBB_U32_e32:
9153-
case AMDGPU::V_SUBB_U32_e64:
9154-
case AMDGPU::V_SUBB_U32_e64_dpp:
9155-
case AMDGPU::V_SUBB_U32_sdwa:
9156-
//
9157-
case AMDGPU::V_SUBREV_CO_U32_dpp:
9158-
case AMDGPU::V_SUBREV_CO_U32_e32:
9159-
case AMDGPU::V_SUBREV_CO_U32_e64:
9160-
case AMDGPU::V_SUBREV_CO_U32_e64_dpp:
9161-
case AMDGPU::V_SUBREV_CO_U32_sdwa:
9162-
//
9163-
case AMDGPU::V_SUBREV_U32_dpp:
9164-
case AMDGPU::V_SUBREV_U32_e32:
9165-
case AMDGPU::V_SUBREV_U32_e64:
9166-
case AMDGPU::V_SUBREV_U32_e64_dpp:
9167-
case AMDGPU::V_SUBREV_U32_sdwa:
9168-
//
9169-
case AMDGPU::V_SUB_CO_U32_dpp:
9170-
case AMDGPU::V_SUB_CO_U32_e32:
9171-
case AMDGPU::V_SUB_CO_U32_e64:
9172-
case AMDGPU::V_SUB_CO_U32_e64_dpp:
9173-
case AMDGPU::V_SUB_CO_U32_sdwa:
9174-
//
9175-
case AMDGPU::V_SUB_U32_dpp:
9176-
case AMDGPU::V_SUB_U32_e32:
9177-
case AMDGPU::V_SUB_U32_e64:
9178-
case AMDGPU::V_SUB_U32_e64_dpp:
9179-
case AMDGPU::V_SUB_U32_sdwa:
9119+
switch (Opcode) {
9120+
case AMDGPU::V_ADDC_U32_dpp:
9121+
case AMDGPU::V_ADDC_U32_e32:
9122+
case AMDGPU::V_ADDC_U32_e64:
9123+
case AMDGPU::V_ADDC_U32_e64_dpp:
9124+
case AMDGPU::V_ADDC_U32_sdwa:
9125+
//
9126+
case AMDGPU::V_ADD_CO_U32_dpp:
9127+
case AMDGPU::V_ADD_CO_U32_e32:
9128+
case AMDGPU::V_ADD_CO_U32_e64:
9129+
case AMDGPU::V_ADD_CO_U32_e64_dpp:
9130+
case AMDGPU::V_ADD_CO_U32_sdwa:
9131+
//
9132+
case AMDGPU::V_ADD_U32_dpp:
9133+
case AMDGPU::V_ADD_U32_e32:
9134+
case AMDGPU::V_ADD_U32_e64:
9135+
case AMDGPU::V_ADD_U32_e64_dpp:
9136+
case AMDGPU::V_ADD_U32_sdwa:
9137+
//
9138+
case AMDGPU::V_DIV_FIXUP_F16_gfx9_e64:
9139+
case AMDGPU::V_FMA_F16_gfx9_e64:
9140+
case AMDGPU::V_INTERP_P2_F16:
9141+
case AMDGPU::V_MAD_F16_e64:
9142+
case AMDGPU::V_MAD_U16_e64:
9143+
case AMDGPU::V_MAD_I16_e64:
9144+
//
9145+
case AMDGPU::V_SUBBREV_U32_dpp:
9146+
case AMDGPU::V_SUBBREV_U32_e32:
9147+
case AMDGPU::V_SUBBREV_U32_e64:
9148+
case AMDGPU::V_SUBBREV_U32_e64_dpp:
9149+
case AMDGPU::V_SUBBREV_U32_sdwa:
9150+
//
9151+
case AMDGPU::V_SUBB_U32_dpp:
9152+
case AMDGPU::V_SUBB_U32_e32:
9153+
case AMDGPU::V_SUBB_U32_e64:
9154+
case AMDGPU::V_SUBB_U32_e64_dpp:
9155+
case AMDGPU::V_SUBB_U32_sdwa:
9156+
//
9157+
case AMDGPU::V_SUBREV_CO_U32_dpp:
9158+
case AMDGPU::V_SUBREV_CO_U32_e32:
9159+
case AMDGPU::V_SUBREV_CO_U32_e64:
9160+
case AMDGPU::V_SUBREV_CO_U32_e64_dpp:
9161+
case AMDGPU::V_SUBREV_CO_U32_sdwa:
9162+
//
9163+
case AMDGPU::V_SUBREV_U32_dpp:
9164+
case AMDGPU::V_SUBREV_U32_e32:
9165+
case AMDGPU::V_SUBREV_U32_e64:
9166+
case AMDGPU::V_SUBREV_U32_e64_dpp:
9167+
case AMDGPU::V_SUBREV_U32_sdwa:
9168+
//
9169+
case AMDGPU::V_SUB_CO_U32_dpp:
9170+
case AMDGPU::V_SUB_CO_U32_e32:
9171+
case AMDGPU::V_SUB_CO_U32_e64:
9172+
case AMDGPU::V_SUB_CO_U32_e64_dpp:
9173+
case AMDGPU::V_SUB_CO_U32_sdwa:
9174+
//
9175+
case AMDGPU::V_SUB_U32_dpp:
9176+
case AMDGPU::V_SUB_U32_e32:
9177+
case AMDGPU::V_SUB_U32_e64:
9178+
case AMDGPU::V_SUB_U32_e64_dpp:
9179+
case AMDGPU::V_SUB_U32_sdwa:
91809180
return true;
91819181
default:
91829182
return false;
@@ -9188,10 +9188,9 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
91889188

91899189
unsigned Gen = subtargetEncodingFamily(ST);
91909190

9191-
if (isRenamedInGFX9(Opcode) &&
9192-
ST.getGeneration() == AMDGPUSubtarget::GFX9){
9191+
if (isRenamedInGFX9(Opcode) && ST.getGeneration() == AMDGPUSubtarget::GFX9) {
91939192
Gen = SIEncodingFamily::GFX9;
9194-
}
9193+
}
91959194

91969195
// Adjust the encoding family to GFX80 for D16 buffer instructions when the
91979196
// subtarget has UnpackedD16VMem feature.

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1340,7 +1340,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
13401340
bool isAsmOnlyOpcode(int MCOp) const;
13411341

13421342
bool isRenamedInGFX9(int Opcode) const;
1343-
1343+
13441344
const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
13451345
const TargetRegisterInfo *TRI,
13461346
const MachineFunction &MF)

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