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remove renamedInGFX9 bit and move check into SIInstrInfo helper function
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5 files changed

+125
-78
lines changed

5 files changed

+125
-78
lines changed

‎llvm/lib/Target/AMDGPU/SIInstrFormats.td

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -84,10 +84,6 @@ class InstSI <dag outs, dag ins, string asm = "",
8484
// Is it possible for this instruction to be atomic?
8585
field bit maybeAtomic = 1;
8686

87-
// This bit indicates that this is a VI instruction which is renamed
88-
// in GFX9. Required for correct mapping from pseudo to MC.
89-
field bit renamedInGFX9 = 0;
90-
9187
// This bit indicates that this has a floating point result type, so
9288
// the clamp modifier has floating point semantics.
9389
field bit FPClamp = 0;
@@ -214,7 +210,9 @@ class InstSI <dag outs, dag ins, string asm = "",
214210
let TSFlags{42} = VOP3_OPSEL;
215211

216212
let TSFlags{43} = maybeAtomic;
217-
let TSFlags{44} = renamedInGFX9;
213+
214+
// Reserved, must be 0.
215+
let TSFlags{44} = 0;
218216

219217
let TSFlags{45} = FPClamp;
220218
let TSFlags{46} = IntClamp;

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 71 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9115,14 +9115,83 @@ bool SIInstrInfo::isAsmOnlyOpcode(int MCOp) const {
91159115
}
91169116
}
91179117

9118+
bool SIInstrInfo::isRenamedInGFX9(int Opcode) const {
9119+
switch(Opcode) {
9120+
case AMDGPU::V_ADDC_U32_dpp:
9121+
case AMDGPU::V_ADDC_U32_e32:
9122+
case AMDGPU::V_ADDC_U32_e64:
9123+
case AMDGPU::V_ADDC_U32_e64_dpp:
9124+
case AMDGPU::V_ADDC_U32_sdwa:
9125+
//
9126+
case AMDGPU::V_ADD_CO_U32_dpp:
9127+
case AMDGPU::V_ADD_CO_U32_e32:
9128+
case AMDGPU::V_ADD_CO_U32_e64:
9129+
case AMDGPU::V_ADD_CO_U32_e64_dpp:
9130+
case AMDGPU::V_ADD_CO_U32_sdwa:
9131+
//
9132+
case AMDGPU::V_ADD_U32_dpp:
9133+
case AMDGPU::V_ADD_U32_e32:
9134+
case AMDGPU::V_ADD_U32_e64:
9135+
case AMDGPU::V_ADD_U32_e64_dpp:
9136+
case AMDGPU::V_ADD_U32_sdwa:
9137+
//
9138+
case AMDGPU::V_DIV_FIXUP_F16_gfx9_e64:
9139+
case AMDGPU::V_FMA_F16_gfx9_e64:
9140+
case AMDGPU::V_INTERP_P2_F16:
9141+
case AMDGPU::V_MAD_F16_e64:
9142+
case AMDGPU::V_MAD_U16_e64:
9143+
case AMDGPU::V_MAD_I16_e64:
9144+
//
9145+
case AMDGPU::V_SUBBREV_U32_dpp:
9146+
case AMDGPU::V_SUBBREV_U32_e32:
9147+
case AMDGPU::V_SUBBREV_U32_e64:
9148+
case AMDGPU::V_SUBBREV_U32_e64_dpp:
9149+
case AMDGPU::V_SUBBREV_U32_sdwa:
9150+
//
9151+
case AMDGPU::V_SUBB_U32_dpp:
9152+
case AMDGPU::V_SUBB_U32_e32:
9153+
case AMDGPU::V_SUBB_U32_e64:
9154+
case AMDGPU::V_SUBB_U32_e64_dpp:
9155+
case AMDGPU::V_SUBB_U32_sdwa:
9156+
//
9157+
case AMDGPU::V_SUBREV_CO_U32_dpp:
9158+
case AMDGPU::V_SUBREV_CO_U32_e32:
9159+
case AMDGPU::V_SUBREV_CO_U32_e64:
9160+
case AMDGPU::V_SUBREV_CO_U32_e64_dpp:
9161+
case AMDGPU::V_SUBREV_CO_U32_sdwa:
9162+
//
9163+
case AMDGPU::V_SUBREV_U32_dpp:
9164+
case AMDGPU::V_SUBREV_U32_e32:
9165+
case AMDGPU::V_SUBREV_U32_e64:
9166+
case AMDGPU::V_SUBREV_U32_e64_dpp:
9167+
case AMDGPU::V_SUBREV_U32_sdwa:
9168+
//
9169+
case AMDGPU::V_SUB_CO_U32_dpp:
9170+
case AMDGPU::V_SUB_CO_U32_e32:
9171+
case AMDGPU::V_SUB_CO_U32_e64:
9172+
case AMDGPU::V_SUB_CO_U32_e64_dpp:
9173+
case AMDGPU::V_SUB_CO_U32_sdwa:
9174+
//
9175+
case AMDGPU::V_SUB_U32_dpp:
9176+
case AMDGPU::V_SUB_U32_e32:
9177+
case AMDGPU::V_SUB_U32_e64:
9178+
case AMDGPU::V_SUB_U32_e64_dpp:
9179+
case AMDGPU::V_SUB_U32_sdwa:
9180+
return true;
9181+
default:
9182+
return false;
9183+
}
9184+
}
9185+
91189186
int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
91199187
Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(Opcode);
91209188

91219189
unsigned Gen = subtargetEncodingFamily(ST);
91229190

9123-
if ((get(Opcode).TSFlags & SIInstrFlags::renamedInGFX9) != 0 &&
9124-
ST.getGeneration() == AMDGPUSubtarget::GFX9)
9191+
if (isRenamedInGFX9(Opcode) &&
9192+
ST.getGeneration() == AMDGPUSubtarget::GFX9){
91259193
Gen = SIEncodingFamily::GFX9;
9194+
}
91269195

91279196
// Adjust the encoding family to GFX80 for D16 buffer instructions when the
91289197
// subtarget has UnpackedD16VMem feature.

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1339,6 +1339,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
13391339
/// Return true if this opcode should not be used by codegen.
13401340
bool isAsmOnlyOpcode(int MCOp) const;
13411341

1342+
bool isRenamedInGFX9(int Opcode) const;
1343+
13421344
const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
13431345
const TargetRegisterInfo *TRI,
13441346
const MachineFunction &MF)

‎llvm/lib/Target/AMDGPU/VOP2Instructions.td

Lines changed: 29 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -141,72 +141,59 @@ class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
141141
multiclass VOP2Inst_e32<string opName,
142142
VOPProfile P,
143143
SDPatternOperator node = null_frag,
144-
string revOp = opName,
145-
bit GFX9Renamed = 0> {
146-
let renamedInGFX9 = GFX9Renamed in {
144+
string revOp = opName> {
147145
def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
148146
Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
149-
} // End renamedInGFX9 = GFX9Renamed
150147
}
151148
multiclass
152149
VOP2Inst_e32_VOPD<string opName, VOPProfile P, bits<5> VOPDOp,
153150
string VOPDName, SDPatternOperator node = null_frag,
154-
string revOp = opName, bit GFX9Renamed = 0> {
155-
defm NAME : VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>,
151+
string revOp = opName> {
152+
defm NAME : VOP2Inst_e32<opName, P, node, revOp>,
156153
VOPD_Component<VOPDOp, VOPDName>;
157154
}
158155
multiclass VOP2Inst_e64<string opName,
159156
VOPProfile P,
160157
SDPatternOperator node = null_frag,
161-
string revOp = opName,
162-
bit GFX9Renamed = 0> {
163-
let renamedInGFX9 = GFX9Renamed in {
158+
string revOp = opName> {
164159
def _e64 : VOP3InstBase <opName, P, node, 1>,
165160
Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
166161

167162
let SubtargetPredicate = isGFX11Plus in {
168163
if P.HasExtVOP3DPP then
169164
def _e64_dpp : VOP3_DPP_Pseudo <opName, P>;
170165
} // End SubtargetPredicate = isGFX11Plus
171-
} // End renamedInGFX9 = GFX9Renamed
172166
}
173167

174168
multiclass VOP2Inst_sdwa<string opName,
175-
VOPProfile P,
176-
bit GFX9Renamed = 0> {
177-
let renamedInGFX9 = GFX9Renamed in {
169+
VOPProfile P> {
178170
if P.HasExtSDWA then
179171
def _sdwa : VOP2_SDWA_Pseudo <opName, P>;
180-
} // End renamedInGFX9 = GFX9Renamed
181172
}
182173

183174
multiclass VOP2Inst<string opName,
184175
VOPProfile P,
185176
SDPatternOperator node = null_frag,
186-
string revOp = opName,
187-
bit GFX9Renamed = 0> :
188-
VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>,
189-
VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>,
190-
VOP2Inst_sdwa<opName, P, GFX9Renamed> {
191-
let renamedInGFX9 = GFX9Renamed in {
177+
string revOp = opName> :
178+
VOP2Inst_e32<opName, P, node, revOp>,
179+
VOP2Inst_e64<opName, P, node, revOp>,
180+
VOP2Inst_sdwa<opName, P> {
192181
if P.HasExtDPP then
193182
def _dpp : VOP2_DPP_Pseudo <opName, P>;
194-
}
195183
}
196184

197185
multiclass VOP2Inst_t16<string opName,
198186
VOPProfile P,
199187
SDPatternOperator node = null_frag,
200-
string revOp = opName,
201-
bit GFX9Renamed = 0> {
188+
string revOp = opName> {
202189
let SubtargetPredicate = NotHasTrue16BitInsts, OtherPredicates = [Has16BitInsts] in {
203-
defm NAME : VOP2Inst<opName, P, node, revOp, GFX9Renamed>;
190+
defm NAME : VOP2Inst<opName, P, node, revOp>;
204191
}
205192
let SubtargetPredicate = UseRealTrue16Insts in {
206-
defm _t16 : VOP2Inst<opName#"_t16", VOPProfile_True16<P>, node, revOp#"_t16", GFX9Renamed>;
193+
defm _t16 : VOP2Inst<opName#"_t16", VOPProfile_True16<P>, node, revOp#"_t16">;
207194
}
208195
let SubtargetPredicate = UseFakeTrue16Insts in {
209-
defm _fake16 : VOP2Inst<opName#"_fake16", VOPProfile_Fake16<P>, node, revOp#"_fake16", GFX9Renamed>;
196+
defm _fake16 : VOP2Inst<opName#"_fake16", VOPProfile_Fake16<P>, node, revOp#"_fake16">;
210197
}
211198
}
212199

@@ -217,13 +204,12 @@ multiclass VOP2Inst_t16<string opName,
217204
multiclass VOP2Inst_e64_t16<string opName,
218205
VOPProfile P,
219206
SDPatternOperator node = null_frag,
220-
string revOp = opName,
221-
bit GFX9Renamed = 0> {
207+
string revOp = opName> {
222208
let SubtargetPredicate = NotHasTrue16BitInsts, OtherPredicates = [Has16BitInsts] in {
223-
defm NAME : VOP2Inst<opName, P, node, revOp, GFX9Renamed>;
209+
defm NAME : VOP2Inst<opName, P, node, revOp>;
224210
}
225211
let SubtargetPredicate = HasTrue16BitInsts in {
226-
defm _t16 : VOP2Inst_e64<opName#"_t16", VOPProfile_Fake16<P>, node, revOp#"_t16", GFX9Renamed>;
212+
defm _t16 : VOP2Inst_e64<opName#"_t16", VOPProfile_Fake16<P>, node, revOp#"_t16">;
227213
}
228214
}
229215

@@ -232,24 +218,19 @@ multiclass VOP2Inst_VOPD<string opName,
232218
bits<5> VOPDOp,
233219
string VOPDName,
234220
SDPatternOperator node = null_frag,
235-
string revOp = opName,
236-
bit GFX9Renamed = 0> :
237-
VOP2Inst_e32_VOPD<opName, P, VOPDOp, VOPDName, node, revOp, GFX9Renamed>,
238-
VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>,
239-
VOP2Inst_sdwa<opName, P, GFX9Renamed> {
240-
let renamedInGFX9 = GFX9Renamed in {
221+
string revOp = opName> :
222+
VOP2Inst_e32_VOPD<opName, P, VOPDOp, VOPDName, node, revOp>,
223+
VOP2Inst_e64<opName, P, node, revOp>,
224+
VOP2Inst_sdwa<opName, P> {
241225
if P.HasExtDPP then
242226
def _dpp : VOP2_DPP_Pseudo <opName, P>;
243-
}
244227
}
245228

246229
multiclass VOP2bInst <string opName,
247230
VOPProfile P,
248231
SDPatternOperator node = null_frag,
249232
string revOp = opName,
250-
bit GFX9Renamed = 0,
251233
bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
252-
let renamedInGFX9 = GFX9Renamed in {
253234
let SchedRW = [Write32Bit, WriteSALU] in {
254235
let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
255236
def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
@@ -273,7 +254,6 @@ multiclass VOP2bInst <string opName,
273254
def _e64_dpp : VOP3_DPP_Pseudo <opName, P>;
274255
} // End SubtargetPredicate = isGFX11Plus
275256
}
276-
}
277257
}
278258

279259
class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst,
@@ -751,18 +731,18 @@ def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>;
751731

752732
// No patterns so that the scalar instructions are always selected.
753733
// The scalar versions will be replaced with vector when needed later.
754-
defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32", 1>;
755-
defm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
756-
defm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
757-
defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>;
758-
defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
759-
defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
734+
defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32">;
735+
defm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32">;
736+
defm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32">;
737+
defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32">;
738+
defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32">;
739+
defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32">;
760740

761741

762742
let SubtargetPredicate = HasAddNoCarryInsts, isReMaterializable = 1 in {
763-
defm V_ADD_U32 : VOP2Inst_VOPD <"v_add_u32", VOP_I32_I32_I32_ARITH, 0x10, "v_add_nc_u32", null_frag, "v_add_u32", 1>;
764-
defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
765-
defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
743+
defm V_ADD_U32 : VOP2Inst_VOPD <"v_add_u32", VOP_I32_I32_I32_ARITH, 0x10, "v_add_nc_u32", null_frag, "v_add_u32">;
744+
defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32">;
745+
defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32">;
766746
}
767747

768748
} // End isCommutable = 1

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td

Lines changed: 20 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -333,35 +333,33 @@ let FPDPRounding = 1 in {
333333
defm V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, any_fma>;
334334
} // End Predicates = [Has16BitInsts, isGFX8Only]
335335

336-
let renamedInGFX9 = 1, SubtargetPredicate = isGFX9Plus in {
336+
let SubtargetPredicate = isGFX9Plus in {
337337
defm V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9",
338338
VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup>;
339339
defm V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, any_fma>;
340-
} // End renamedInGFX9 = 1, SubtargetPredicate = isGFX9Plus
340+
} // End SubtargetPredicate = isGFX9Plus
341341
} // End FPDPRounding = 1
342342

343343
let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in {
344344

345-
let renamedInGFX9 = 1 in {
346-
defm V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
347-
defm V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
348-
let FPDPRounding = 1 in {
349-
defm V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, any_fmad>;
350-
let Uses = [MODE, M0, EXEC] in {
351-
let OtherPredicates = [isNotGFX90APlus] in
352-
// For some reason the intrinsic operands are in a different order
353-
// from the instruction operands.
354-
def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>,
355-
[(set f16:$vdst,
356-
(int_amdgcn_interp_p2_f16 (VOP3Mods f32:$src2, i32:$src2_modifiers),
357-
(VOP3Mods f32:$src0, i32:$src0_modifiers),
358-
(i32 timm:$attrchan),
359-
(i32 timm:$attr),
360-
(i1 timm:$high),
361-
M0))]>;
362-
} // End Uses = [M0, MODE, EXEC]
363-
} // End FPDPRounding = 1
364-
} // End renamedInGFX9 = 1
345+
defm V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
346+
defm V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
347+
let FPDPRounding = 1 in {
348+
defm V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, any_fmad>;
349+
let Uses = [MODE, M0, EXEC] in {
350+
let OtherPredicates = [isNotGFX90APlus] in
351+
// For some reason the intrinsic operands are in a different order
352+
// from the instruction operands.
353+
def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>,
354+
[(set f16:$vdst,
355+
(int_amdgcn_interp_p2_f16 (VOP3Mods f32:$src2, i32:$src2_modifiers),
356+
(VOP3Mods f32:$src0, i32:$src0_modifiers),
357+
(i32 timm:$attrchan),
358+
(i32 timm:$attr),
359+
(i1 timm:$high),
360+
M0))]>;
361+
} // End Uses = [M0, MODE, EXEC]
362+
} // End FPDPRounding = 1
365363

366364
let SubtargetPredicate = isGFX9Only, FPDPRounding = 1 in {
367365
defm V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>> ;

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