Update AddrType cond

Author: mariusz-sikora-at-amd

llvm/lib/Target/AMDGPU/MIMGInstructions.td

@@ -1517,10 +1517,10 @@ class MIMG_IntersectRay_Helper<bit Is64, bit IsA16, bit isDual, bit isBVH8> {
   int GFX11PlusNSAAddrs = !if(IsA16, 4, 5);
   RegisterClass node_ptr_type = !if(Is64, VReg_64, VGPR_32);
   list<RegisterClass> GFX11PlusAddrTypes =
-     !cond(!eq(isBVH8, 1) : [node_ptr_type, VReg_64, VReg_96, VReg_96, VGPR_32],
-           !eq(isDual, 1) : [node_ptr_type, VReg_64, VReg_96, VReg_96, VReg_64],
-           !eq(IsA16,  0) : [node_ptr_type, VGPR_32, VReg_96, VReg_96, VReg_96],
-           !eq(IsA16,  1) : [node_ptr_type, VGPR_32, VReg_96, VReg_96]);
+     !cond(isBVH8 : [node_ptr_type, VReg_64, VReg_96, VReg_96, VGPR_32],
+           isDual : [node_ptr_type, VReg_64, VReg_96, VReg_96, VReg_64],
+           IsA16  : [node_ptr_type, VGPR_32, VReg_96, VReg_96],
+           true   : [node_ptr_type, VGPR_32, VReg_96, VReg_96, VReg_96]);
 }
 
 class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC>