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Revert "[AArch64] NFC: rename subreg zsub to qsub (#111154)"
This caused asserts to fire: (Subtarget.isSVEorStreamingSVEAvailable() && "Unexpected register store without SVE store instructions"), function storeRegToStackSlot, file AArch64InstrInfo.cpp, line 5346. See comment on the PR for reproducer. This reverts commit 9fd15ad.
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3 files changed

+16
-16
lines changed

3 files changed

+16
-16
lines changed

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ let Namespace = "AArch64" in {
3030
def sube64 : SubRegIndex<64>;
3131
def subo64 : SubRegIndex<64>;
3232
// SVE
33-
def qsub : SubRegIndex<128>;
33+
def zsub : SubRegIndex<128>;
3434
// Note: Code depends on these having consecutive numbers
3535
def dsub0 : SubRegIndex<64>;
3636
def dsub1 : SubRegIndex<64>;
@@ -857,7 +857,7 @@ let SubRegIndices = [psub] in {
857857
}
858858

859859
// SVE variable-size vector registers
860-
let SubRegIndices = [qsub] in {
860+
let SubRegIndices = [zsub] in {
861861
def Z0 : AArch64Reg<0, "z0", [Q0]>, DwarfRegNum<[96]>;
862862
def Z1 : AArch64Reg<1, "z1", [Q1]>, DwarfRegNum<[97]>;
863863
def Z2 : AArch64Reg<2, "z2", [Q2]>, DwarfRegNum<[98]>;

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2003,9 +2003,9 @@ let Predicates = [HasSVEorSME] in {
20032003
// extract/insert 128-bit fixed length vector from/into a scalable vector
20042004
foreach VT = [v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64, v8bf16] in {
20052005
def : Pat<(VT (vector_extract_subvec NEONType<VT>.SVEContainer:$Zs, (i64 0))),
2006-
(EXTRACT_SUBREG ZPR:$Zs, qsub)>;
2006+
(EXTRACT_SUBREG ZPR:$Zs, zsub)>;
20072007
def : Pat<(NEONType<VT>.SVEContainer (vector_insert_subvec undef, (VT V128:$src), (i64 0))),
2008-
(INSERT_SUBREG (IMPLICIT_DEF), $src, qsub)>;
2008+
(INSERT_SUBREG (IMPLICIT_DEF), $src, zsub)>;
20092009
}
20102010

20112011
// Concatenate two predicates.
@@ -3358,28 +3358,28 @@ let Predicates = [HasSVEorSME] in {
33583358
// Extract element from vector with immediate index that's within the bottom 128-bits.
33593359
let Predicates = [HasNEON], AddedComplexity = 1 in {
33603360
def : Pat<(i32 (vector_extract nxv16i8:$vec, VectorIndexB:$index)),
3361-
(UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexB:$index)>;
3361+
(UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>;
33623362
def : Pat<(i32 (vector_extract nxv8i16:$vec, VectorIndexH:$index)),
3363-
(UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexH:$index)>;
3363+
(UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>;
33643364
def : Pat<(i32 (vector_extract nxv4i32:$vec, VectorIndexS:$index)),
3365-
(UMOVvi32 (v4i32 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexS:$index)>;
3365+
(UMOVvi32 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>;
33663366
def : Pat<(i64 (vector_extract nxv2i64:$vec, VectorIndexD:$index)),
3367-
(UMOVvi64 (v2i64 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexD:$index)>;
3367+
(UMOVvi64 (v2i64 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexD:$index)>;
33683368
} // End HasNEON
33693369

33703370
let Predicates = [HasNEON] in {
33713371
def : Pat<(sext_inreg (vector_extract nxv16i8:$vec, VectorIndexB:$index), i8),
3372-
(SMOVvi8to32 (v16i8 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexB:$index)>;
3372+
(SMOVvi8to32 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>;
33733373
def : Pat<(sext_inreg (anyext (i32 (vector_extract nxv16i8:$vec, VectorIndexB:$index))), i8),
3374-
(SMOVvi8to64 (v16i8 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexB:$index)>;
3374+
(SMOVvi8to64 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>;
33753375

33763376
def : Pat<(sext_inreg (vector_extract nxv8i16:$vec, VectorIndexH:$index), i16),
3377-
(SMOVvi16to32 (v8i16 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexH:$index)>;
3377+
(SMOVvi16to32 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>;
33783378
def : Pat<(sext_inreg (anyext (i32 (vector_extract nxv8i16:$vec, VectorIndexH:$index))), i16),
3379-
(SMOVvi16to64 (v8i16 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexH:$index)>;
3379+
(SMOVvi16to64 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>;
33803380

33813381
def : Pat<(sext (i32 (vector_extract nxv4i32:$vec, VectorIndexS:$index))),
3382-
(SMOVvi32to64 (v4i32 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexS:$index)>;
3382+
(SMOVvi32to64 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>;
33833383
} // End HasNEON
33843384

33853385
// Extract first element from vector.

‎llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ define void @dont_coalesce_args(<2 x i64> %a) "aarch64_pstate_sm_body" nounwind
1313
; CHECK-COALESCER-BARRIER-NEXT: [[COALESCER_BARRIER_FPR128_:%[0-9]+]]:fpr128 = COALESCER_BARRIER_FPR128 [[COPY]]
1414
; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg
1515
; CHECK-COALESCER-BARRIER-NEXT: [[DEF:%[0-9]+]]:zpr = IMPLICIT_DEF
16-
; CHECK-COALESCER-BARRIER-NEXT: [[INSERT_SUBREG:%[0-9]+]]:zpr = INSERT_SUBREG [[DEF]], [[COALESCER_BARRIER_FPR128_]], %subreg.qsub
16+
; CHECK-COALESCER-BARRIER-NEXT: [[INSERT_SUBREG:%[0-9]+]]:zpr = INSERT_SUBREG [[DEF]], [[COALESCER_BARRIER_FPR128_]], %subreg.zsub
1717
; CHECK-COALESCER-BARRIER-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
1818
; CHECK-COALESCER-BARRIER-NEXT: $z0 = COPY [[INSERT_SUBREG]]
1919
; CHECK-COALESCER-BARRIER-NEXT: BL @scalable_args, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
@@ -47,7 +47,7 @@ define <2 x i64> @dont_coalesce_res() "aarch64_pstate_sm_body" nounwind {
4747
; CHECK-COALESCER-BARRIER-NEXT: BL @scalable_res, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $z0
4848
; CHECK-COALESCER-BARRIER-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
4949
; CHECK-COALESCER-BARRIER-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
50-
; CHECK-COALESCER-BARRIER-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY [[COPY]].qsub
50+
; CHECK-COALESCER-BARRIER-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY [[COPY]].zsub
5151
; CHECK-COALESCER-BARRIER-NEXT: [[COALESCER_BARRIER_FPR128_:%[0-9]+]]:fpr128 = COALESCER_BARRIER_FPR128 [[COPY1]]
5252
; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $q0, implicit $vg, implicit-def $vg
5353
; CHECK-COALESCER-BARRIER-NEXT: $q0 = COPY [[COALESCER_BARRIER_FPR128_]]
@@ -78,7 +78,7 @@ define <2 x i64> @dont_coalesce_arg_that_is_also_res(<2 x i64> %a) "aarch64_psta
7878
; CHECK-COALESCER-BARRIER-NEXT: [[COALESCER_BARRIER_FPR128_:%[0-9]+]]:fpr128 = COALESCER_BARRIER_FPR128 [[COPY]]
7979
; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg
8080
; CHECK-COALESCER-BARRIER-NEXT: [[DEF:%[0-9]+]]:zpr = IMPLICIT_DEF
81-
; CHECK-COALESCER-BARRIER-NEXT: [[INSERT_SUBREG:%[0-9]+]]:zpr = INSERT_SUBREG [[DEF]], [[COALESCER_BARRIER_FPR128_]], %subreg.qsub
81+
; CHECK-COALESCER-BARRIER-NEXT: [[INSERT_SUBREG:%[0-9]+]]:zpr = INSERT_SUBREG [[DEF]], [[COALESCER_BARRIER_FPR128_]], %subreg.zsub
8282
; CHECK-COALESCER-BARRIER-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
8383
; CHECK-COALESCER-BARRIER-NEXT: $z0 = COPY [[INSERT_SUBREG]]
8484
; CHECK-COALESCER-BARRIER-NEXT: BL @scalable_args, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp

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