[AArch64] NFC: rename subreg zsub to qsub #111154
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I believe this is more correct, because 'dsub' represents the lower 64 bits in a 128 bit register. Similarly, I would expect 'qsub' to represent the lower 128 bits in a 128+ bit register.
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@llvm/pr-subscribers-backend-aarch64 Author: Sander de Smalen (sdesmalen-arm) ChangesI believe this is more correct, because 'dsub' represents the lower 64 bits in a 128 bit register. Similarly, I would expect 'qsub' to represent the lower 128 bits in a 128+ bit register. Full diff: https://github.com/llvm/llvm-project/pull/111154.diff 3 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index f754c32e1176d1..306d7b39ab0e06 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -30,7 +30,7 @@ let Namespace = "AArch64" in {
def sube64 : SubRegIndex<64>;
def subo64 : SubRegIndex<64>;
// SVE
- def zsub : SubRegIndex<128>;
+ def qsub : SubRegIndex<128>;
// Note: Code depends on these having consecutive numbers
def dsub0 : SubRegIndex<64>;
def dsub1 : SubRegIndex<64>;
@@ -857,7 +857,7 @@ let SubRegIndices = [psub] in {
}
// SVE variable-size vector registers
-let SubRegIndices = [zsub] in {
+let SubRegIndices = [qsub] in {
def Z0 : AArch64Reg<0, "z0", [Q0]>, DwarfRegNum<[96]>;
def Z1 : AArch64Reg<1, "z1", [Q1]>, DwarfRegNum<[97]>;
def Z2 : AArch64Reg<2, "z2", [Q2]>, DwarfRegNum<[98]>;
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 7240f6a22a87bd..2659d8a7b1718d 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1993,9 +1993,9 @@ let Predicates = [HasSVEorSME] in {
// extract/insert 128-bit fixed length vector from/into a scalable vector
foreach VT = [v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64, v8bf16] in {
def : Pat<(VT (vector_extract_subvec NEONType<VT>.SVEContainer:$Zs, (i64 0))),
- (EXTRACT_SUBREG ZPR:$Zs, zsub)>;
+ (EXTRACT_SUBREG ZPR:$Zs, qsub)>;
def : Pat<(NEONType<VT>.SVEContainer (vector_insert_subvec undef, (VT V128:$src), (i64 0))),
- (INSERT_SUBREG (IMPLICIT_DEF), $src, zsub)>;
+ (INSERT_SUBREG (IMPLICIT_DEF), $src, qsub)>;
}
// Concatenate two predicates.
@@ -3348,28 +3348,28 @@ let Predicates = [HasSVEorSME] in {
// Extract element from vector with immediate index that's within the bottom 128-bits.
let Predicates = [HasNEON], AddedComplexity = 1 in {
def : Pat<(i32 (vector_extract nxv16i8:$vec, VectorIndexB:$index)),
- (UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>;
+ (UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexB:$index)>;
def : Pat<(i32 (vector_extract nxv8i16:$vec, VectorIndexH:$index)),
- (UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>;
+ (UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexH:$index)>;
def : Pat<(i32 (vector_extract nxv4i32:$vec, VectorIndexS:$index)),
- (UMOVvi32 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>;
+ (UMOVvi32 (v4i32 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexS:$index)>;
def : Pat<(i64 (vector_extract nxv2i64:$vec, VectorIndexD:$index)),
- (UMOVvi64 (v2i64 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexD:$index)>;
+ (UMOVvi64 (v2i64 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexD:$index)>;
} // End HasNEON
let Predicates = [HasNEON] in {
def : Pat<(sext_inreg (vector_extract nxv16i8:$vec, VectorIndexB:$index), i8),
- (SMOVvi8to32 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>;
+ (SMOVvi8to32 (v16i8 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexB:$index)>;
def : Pat<(sext_inreg (anyext (i32 (vector_extract nxv16i8:$vec, VectorIndexB:$index))), i8),
- (SMOVvi8to64 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>;
+ (SMOVvi8to64 (v16i8 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexB:$index)>;
def : Pat<(sext_inreg (vector_extract nxv8i16:$vec, VectorIndexH:$index), i16),
- (SMOVvi16to32 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>;
+ (SMOVvi16to32 (v8i16 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexH:$index)>;
def : Pat<(sext_inreg (anyext (i32 (vector_extract nxv8i16:$vec, VectorIndexH:$index))), i16),
- (SMOVvi16to64 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>;
+ (SMOVvi16to64 (v8i16 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexH:$index)>;
def : Pat<(sext (i32 (vector_extract nxv4i32:$vec, VectorIndexS:$index))),
- (SMOVvi32to64 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>;
+ (SMOVvi32to64 (v4i32 (EXTRACT_SUBREG ZPR:$vec, qsub)), VectorIndexS:$index)>;
} // End HasNEON
// Extract first element from vector.
diff --git a/llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll b/llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll
index 8e3866fcec89a7..22e2f4be21078a 100644
--- a/llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll
+++ b/llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll
@@ -13,7 +13,7 @@ define void @dont_coalesce_args(<2 x i64> %a) "aarch64_pstate_sm_body" nounwind
; CHECK-COALESCER-BARRIER-NEXT: [[COALESCER_BARRIER_FPR128_:%[0-9]+]]:fpr128 = COALESCER_BARRIER_FPR128 [[COPY]]
; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg
; CHECK-COALESCER-BARRIER-NEXT: [[DEF:%[0-9]+]]:zpr = IMPLICIT_DEF
- ; CHECK-COALESCER-BARRIER-NEXT: [[INSERT_SUBREG:%[0-9]+]]:zpr = INSERT_SUBREG [[DEF]], [[COALESCER_BARRIER_FPR128_]], %subreg.zsub
+ ; CHECK-COALESCER-BARRIER-NEXT: [[INSERT_SUBREG:%[0-9]+]]:zpr = INSERT_SUBREG [[DEF]], [[COALESCER_BARRIER_FPR128_]], %subreg.qsub
; CHECK-COALESCER-BARRIER-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-COALESCER-BARRIER-NEXT: $z0 = COPY [[INSERT_SUBREG]]
; CHECK-COALESCER-BARRIER-NEXT: BL @scalable_args, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
@@ -47,7 +47,7 @@ define <2 x i64> @dont_coalesce_res() "aarch64_pstate_sm_body" nounwind {
; CHECK-COALESCER-BARRIER-NEXT: BL @scalable_res, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $z0
; CHECK-COALESCER-BARRIER-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-COALESCER-BARRIER-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
- ; CHECK-COALESCER-BARRIER-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY [[COPY]].zsub
+ ; CHECK-COALESCER-BARRIER-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY [[COPY]].qsub
; CHECK-COALESCER-BARRIER-NEXT: [[COALESCER_BARRIER_FPR128_:%[0-9]+]]:fpr128 = COALESCER_BARRIER_FPR128 [[COPY1]]
; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $q0, implicit $vg, implicit-def $vg
; CHECK-COALESCER-BARRIER-NEXT: $q0 = COPY [[COALESCER_BARRIER_FPR128_]]
@@ -78,7 +78,7 @@ define <2 x i64> @dont_coalesce_arg_that_is_also_res(<2 x i64> %a) "aarch64_psta
; CHECK-COALESCER-BARRIER-NEXT: [[COALESCER_BARRIER_FPR128_:%[0-9]+]]:fpr128 = COALESCER_BARRIER_FPR128 [[COPY]]
; CHECK-COALESCER-BARRIER-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg
; CHECK-COALESCER-BARRIER-NEXT: [[DEF:%[0-9]+]]:zpr = IMPLICIT_DEF
- ; CHECK-COALESCER-BARRIER-NEXT: [[INSERT_SUBREG:%[0-9]+]]:zpr = INSERT_SUBREG [[DEF]], [[COALESCER_BARRIER_FPR128_]], %subreg.zsub
+ ; CHECK-COALESCER-BARRIER-NEXT: [[INSERT_SUBREG:%[0-9]+]]:zpr = INSERT_SUBREG [[DEF]], [[COALESCER_BARRIER_FPR128_]], %subreg.qsub
; CHECK-COALESCER-BARRIER-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK-COALESCER-BARRIER-NEXT: $z0 = COPY [[INSERT_SUBREG]]
; CHECK-COALESCER-BARRIER-NEXT: BL @scalable_args, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
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paulwalker-arm
approved these changes
Oct 4, 2024
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/30/builds/7817 Here is the relevant piece of the build log for the reference |
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We're hitting an assert after this change: See https://crbug.com/372053411#comment3 for a reproducer. I'll prepare a revert until this can be fixed. |
zmodem
added a commit
that referenced
this pull request
Oct 8, 2024
This caused asserts to fire: (Subtarget.isSVEorStreamingSVEAvailable() && "Unexpected register store without SVE store instructions"), function storeRegToStackSlot, file AArch64InstrInfo.cpp, line 5346. See comment on the PR for reproducer. This reverts commit 9fd15ad.
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I believe this is more correct, because 'dsub' represents the lower 64 bits in a 128 bit register. Similarly, I would expect 'qsub' to represent the lower 128 bits in a 128+ bit register.