Extend vXi1 setcc to account for intrinsic VT promotion

Author: SamTebbs33

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

@@ -1800,14 +1800,23 @@ SDValue VectorLegalizer::ExpandLOOP_DEPENDENCE_MASK(SDNode *N) {
 
   // Create the lane mask
   EVT SplatTY =
-      EVT::getVectorVT(*DAG.getContext(), PtrVT, VT.getVectorElementCount());
+      EVT::getVectorVT(*DAG.getContext(), PtrVT, VT.getVectorMinNumElements(),
+                       VT.isScalableVector());
   SDValue DiffSplat = DAG.getSplat(SplatTY, DL, Diff);
   SDValue VectorStep = DAG.getStepVector(DL, SplatTY);
+  EVT MaskVT =
+      EVT::getVectorVT(*DAG.getContext(), MVT::i1, VT.getVectorMinNumElements(),
+                       VT.isScalableVector());
   SDValue DiffMask =
-      DAG.getSetCC(DL, VT, VectorStep, DiffSplat, ISD::CondCode::SETULT);
+      DAG.getSetCC(DL, MaskVT, VectorStep, DiffSplat, ISD::CondCode::SETULT);
 
-  // Splat the compare result then OR it with the lane mask
   EVT VTElementTy = VT.getVectorElementType();
+  // Extend the diff setcc in case the intrinsic has been promoted to a vector
+  // type with elements larger than i1
+  if (VTElementTy.getScalarSizeInBits() > MaskVT.getScalarSizeInBits())
+    DiffMask = DAG.getNode(ISD::ANY_EXTEND, DL, VT, DiffMask);
+
+  // Splat the compare result then OR it with the lane mask
   if (CmpVT.getScalarSizeInBits() < VTElementTy.getScalarSizeInBits())
     Cmp = DAG.getNode(ISD::ZERO_EXTEND, DL, VTElementTy, Cmp);
   SDValue Splat = DAG.getSplat(VT, DL, Cmp);

llvm/test/CodeGen/AArch64/alias_mask.ll

@@ -48,8 +48,6 @@ define <16 x i1> @whilewr_8(ptr %a, ptr %b) {
 ; CHECK-NOSVE-NEXT:    uzp1 v1.8h, v2.8h, v3.8h
 ; CHECK-NOSVE-NEXT:    uzp1 v0.16b, v1.16b, v0.16b
 ; CHECK-NOSVE-NEXT:    dup v1.16b, w8
-; CHECK-NOSVE-NEXT:    shl v0.16b, v0.16b, #7
-; CHECK-NOSVE-NEXT:    cmlt v0.16b, v0.16b, #0
 ; CHECK-NOSVE-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NOSVE-NEXT:    ret
 entry:
@@ -90,8 +88,6 @@ define <8 x i1> @whilewr_16(ptr %a, ptr %b) {
 ; CHECK-NOSVE-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
 ; CHECK-NOSVE-NEXT:    dup v1.8b, w8
 ; CHECK-NOSVE-NEXT:    xtn v0.8b, v0.8h
-; CHECK-NOSVE-NEXT:    shl v0.8b, v0.8b, #7
-; CHECK-NOSVE-NEXT:    cmlt v0.8b, v0.8b, #0
 ; CHECK-NOSVE-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; CHECK-NOSVE-NEXT:    ret
 entry:
@@ -210,8 +206,6 @@ define <16 x i1> @whilerw_8(ptr %a, ptr %b) {
 ; CHECK-NOSVE-NEXT:    uzp1 v1.8h, v3.8h, v2.8h
 ; CHECK-NOSVE-NEXT:    uzp1 v0.16b, v1.16b, v0.16b
 ; CHECK-NOSVE-NEXT:    dup v1.16b, w8
-; CHECK-NOSVE-NEXT:    shl v0.16b, v0.16b, #7
-; CHECK-NOSVE-NEXT:    cmlt v0.16b, v0.16b, #0
 ; CHECK-NOSVE-NEXT:    orr v0.16b, v0.16b, v1.16b
 ; CHECK-NOSVE-NEXT:    ret
 entry:
@@ -253,8 +247,6 @@ define <8 x i1> @whilerw_16(ptr %a, ptr %b) {
 ; CHECK-NOSVE-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
 ; CHECK-NOSVE-NEXT:    dup v1.8b, w8
 ; CHECK-NOSVE-NEXT:    xtn v0.8b, v0.8h
-; CHECK-NOSVE-NEXT:    shl v0.8b, v0.8b, #7
-; CHECK-NOSVE-NEXT:    cmlt v0.8b, v0.8b, #0
 ; CHECK-NOSVE-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; CHECK-NOSVE-NEXT:    ret
 entry: