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[RISCV][GISel] Merge RISCVCallLowering::lowerReturnVal into RISCVCallLowering::lowerReturn. NFC
This is similar to X86 and AArch64 structure.
1 parent 39ec1f7 commit 381a803

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2 files changed

+27
-38
lines changed

2 files changed

+27
-38
lines changed

llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp

Lines changed: 27 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -388,47 +388,39 @@ static bool isSupportedReturnType(Type *T, const RISCVSubtarget &Subtarget,
388388
return false;
389389
}
390390

391-
bool RISCVCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
392-
const Value *Val,
393-
ArrayRef<Register> VRegs,
394-
MachineInstrBuilder &Ret) const {
395-
if (!Val)
396-
return true;
397-
398-
const RISCVSubtarget &Subtarget =
399-
MIRBuilder.getMF().getSubtarget<RISCVSubtarget>();
400-
if (!isSupportedReturnType(Val->getType(), Subtarget, /*IsLowerRetVal=*/true))
401-
return false;
402-
403-
MachineFunction &MF = MIRBuilder.getMF();
404-
const DataLayout &DL = MF.getDataLayout();
405-
const Function &F = MF.getFunction();
406-
CallingConv::ID CC = F.getCallingConv();
407-
408-
ArgInfo OrigRetInfo(VRegs, Val->getType(), 0);
409-
setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
410-
411-
SmallVector<ArgInfo, 4> SplitRetInfos;
412-
splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, CC);
413-
414-
RVVArgDispatcher Dispatcher{&MF, getTLI<RISCVTargetLowering>(),
415-
ArrayRef(F.getReturnType())};
416-
RISCVOutgoingValueAssigner Assigner(
417-
CC == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV,
418-
/*IsRet=*/true, Dispatcher);
419-
RISCVOutgoingValueHandler Handler(MIRBuilder, MF.getRegInfo(), Ret);
420-
return determineAndHandleAssignments(Handler, Assigner, SplitRetInfos,
421-
MIRBuilder, CC, F.isVarArg());
422-
}
423-
424391
bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
425392
const Value *Val, ArrayRef<Register> VRegs,
426393
FunctionLoweringInfo &FLI) const {
427394
assert(!Val == VRegs.empty() && "Return value without a vreg");
428395
MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET);
429396

430-
if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
431-
return false;
397+
if (!VRegs.empty()) {
398+
const RISCVSubtarget &Subtarget =
399+
MIRBuilder.getMF().getSubtarget<RISCVSubtarget>();
400+
if (!isSupportedReturnType(Val->getType(), Subtarget, /*IsLowerRetVal=*/true))
401+
return false;
402+
403+
MachineFunction &MF = MIRBuilder.getMF();
404+
const DataLayout &DL = MF.getDataLayout();
405+
const Function &F = MF.getFunction();
406+
CallingConv::ID CC = F.getCallingConv();
407+
408+
ArgInfo OrigRetInfo(VRegs, Val->getType(), 0);
409+
setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
410+
411+
SmallVector<ArgInfo, 4> SplitRetInfos;
412+
splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, CC);
413+
414+
RVVArgDispatcher Dispatcher{&MF, getTLI<RISCVTargetLowering>(),
415+
ArrayRef(F.getReturnType())};
416+
RISCVOutgoingValueAssigner Assigner(
417+
CC == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV,
418+
/*IsRet=*/true, Dispatcher);
419+
RISCVOutgoingValueHandler Handler(MIRBuilder, MF.getRegInfo(), Ret);
420+
if (!determineAndHandleAssignments(Handler, Assigner, SplitRetInfos,
421+
MIRBuilder, CC, F.isVarArg()))
422+
return false;
423+
}
432424

433425
MIRBuilder.insertInstr(Ret);
434426
return true;

llvm/lib/Target/RISCV/GISel/RISCVCallLowering.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -40,9 +40,6 @@ class RISCVCallLowering : public CallLowering {
4040
CallLoweringInfo &Info) const override;
4141

4242
private:
43-
bool lowerReturnVal(MachineIRBuilder &MIRBuilder, const Value *Val,
44-
ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
45-
4643
void saveVarArgRegisters(MachineIRBuilder &MIRBuilder,
4744
CallLowering::IncomingValueHandler &Handler,
4845
IncomingValueAssigner &Assigner,

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