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1 |
| -; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 |
2 |
| -; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -O0 -stop-after=amdgpu-isel -o - %s | FileCheck --check-prefix=SelDAG %s |
3 |
| -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 -stop-after=legalizer -o - %s | FileCheck --check-prefix=GlobalISel %s |
| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 -o - %s | FileCheck %s |
| 3 | +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 -o - %s | FileCheck %s |
4 | 4 |
|
5 | 5 | declare i32 @llvm.amdgcn.workitem.id.x()
|
6 | 6 | declare i32 @llvm.amdgcn.workitem.id.y()
|
7 | 7 | declare i32 @llvm.amdgcn.workitem.id.z()
|
8 | 8 |
|
9 |
| -define amdgpu_ps void @undefined_workitems(ptr %p, ptr %q, ptr %r) { |
10 |
| - ; SelDAG-LABEL: name: undefined_workitems |
11 |
| - ; SelDAG: bb.0 (%ir-block.0): |
12 |
| - ; SelDAG-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 |
13 |
| - ; SelDAG-NEXT: {{ $}} |
14 |
| - ; SelDAG-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr5 |
15 |
| - ; SelDAG-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr4 |
16 |
| - ; SelDAG-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3 |
17 |
| - ; SelDAG-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 |
18 |
| - ; SelDAG-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
19 |
| - ; SelDAG-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
20 |
| - ; SelDAG-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 |
21 |
| - ; SelDAG-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 |
22 |
| - ; SelDAG-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY4]], %subreg.sub1 |
23 |
| - ; SelDAG-NEXT: [[COPY6:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]] |
24 |
| - ; SelDAG-NEXT: [[COPY7:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]] |
25 |
| - ; SelDAG-NEXT: [[COPY8:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE2]] |
26 |
| - ; SelDAG-NEXT: S_ENDPGM 0 |
27 |
| - ; |
28 |
| - ; GlobalISel-LABEL: name: undefined_workitems |
29 |
| - ; GlobalISel: bb.1 (%ir-block.0): |
30 |
| - ; GlobalISel-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 |
31 |
| - ; GlobalISel-NEXT: {{ $}} |
32 |
| - ; GlobalISel-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
33 |
| - ; GlobalISel-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
34 |
| - ; GlobalISel-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) |
35 |
| - ; GlobalISel-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 |
36 |
| - ; GlobalISel-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 |
37 |
| - ; GlobalISel-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) |
38 |
| - ; GlobalISel-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4 |
39 |
| - ; GlobalISel-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5 |
40 |
| - ; GlobalISel-NEXT: [[MV2:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32) |
41 |
| - ; GlobalISel-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF |
42 |
| - ; GlobalISel-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF]](s32) |
43 |
| - ; GlobalISel-NEXT: G_STORE [[COPY6]](s32), [[MV]](p0) :: (store (s32) into %ir.p) |
44 |
| - ; GlobalISel-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[DEF]](s32) |
45 |
| - ; GlobalISel-NEXT: G_STORE [[COPY7]](s32), [[MV1]](p0) :: (store (s32) into %ir.q) |
46 |
| - ; GlobalISel-NEXT: G_STORE [[DEF]](s32), [[MV2]](p0) :: (store (s32) into %ir.r) |
47 |
| - ; GlobalISel-NEXT: S_ENDPGM 0 |
| 9 | +define amdgpu_ps void @undefined_workitems(ptr addrspace(1) %p, ptr addrspace(1) %q, ptr addrspace(1) %r) { |
| 10 | +; CHECK-LABEL: undefined_workitems: |
| 11 | +; CHECK: ; %bb.0: |
| 12 | +; CHECK-NEXT: s_endpgm |
48 | 13 | %id.x = call i32 @llvm.amdgcn.workitem.id.x()
|
49 |
| - store i32 %id.x, ptr %p |
| 14 | + store i32 %id.x, ptr addrspace(1) %p |
50 | 15 | %id.y = call i32 @llvm.amdgcn.workitem.id.y()
|
51 |
| - store i32 %id.y, ptr %q |
| 16 | + store i32 %id.y, ptr addrspace(1) %q |
52 | 17 | %id.z = call i32 @llvm.amdgcn.workitem.id.z()
|
53 |
| - store i32 %id.z, ptr %r |
| 18 | + store i32 %id.z, ptr addrspace(1) %r |
54 | 19 | ret void
|
55 | 20 | }
|
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