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use multiclass
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3 files changed

+98
-103
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‎llvm/lib/Target/X86/X86InstrKL.td

Lines changed: 39 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -14,14 +14,32 @@
1414

1515
//===----------------------------------------------------------------------===//
1616
// Key Locker instructions
17-
class Encodekey<bits<8> opcode, string mnemonic>
18-
: I<opcode, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), mnemonic#"\t{$src, $dst|$dst, $src}", []>,
17+
class Encodekey<bits<8> opcode, string m>
18+
: I<opcode, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), m#"\t{$src, $dst|$dst, $src}", []>,
1919
NoCD8, XS;
2020

21-
class Aesencdec<bits<8> opcode, string mnemonic, SDNode node>
22-
: I<opcode, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
23-
mnemonic#"\t{$src2, $src1|$src1, $src2}",
24-
[(set VR128:$dst, EFLAGS, (node VR128:$src1, addr:$src2))]>, NoCD8, XS;
21+
multiclass Aesencdec<string suffix> {
22+
def AESENC128KL#suffix : I<0xDC, MRMSrcMem, (outs VR128:$dst),
23+
(ins VR128:$src1, opaquemem:$src2),
24+
"aesenc128kl\t{$src2, $src1|$src1, $src2}",
25+
[(set VR128:$dst, EFLAGS, (X86aesenc128kl VR128:$src1, addr:$src2))]>,
26+
NoCD8, XS;
27+
def AESDEC128KL#suffix : I<0xDD, MRMSrcMem, (outs VR128:$dst),
28+
(ins VR128:$src1, opaquemem:$src2),
29+
"aesdec128kl\t{$src2, $src1|$src1, $src2}",
30+
[(set VR128:$dst, EFLAGS, (X86aesdec128kl VR128:$src1, addr:$src2))]>,
31+
NoCD8, XS;
32+
def AESENC256KL#suffix : I<0xDE, MRMSrcMem, (outs VR128:$dst),
33+
(ins VR128:$src1, opaquemem:$src2),
34+
"aesenc256kl\t{$src2, $src1|$src1, $src2}",
35+
[(set VR128:$dst, EFLAGS, (X86aesenc256kl VR128:$src1, addr:$src2))]>,
36+
NoCD8, XS;
37+
def AESDEC256KL#suffix : I<0xDF, MRMSrcMem, (outs VR128:$dst),
38+
(ins VR128:$src1, opaquemem:$src2),
39+
"aesdec256kl\t{$src2, $src1|$src1, $src2}",
40+
[(set VR128:$dst, EFLAGS, (X86aesdec256kl VR128:$src1, addr:$src2))]>,
41+
NoCD8, XS;
42+
}
2543

2644
let SchedRW = [WriteSystem] in {
2745
let Uses = [XMM0, EAX], Defs = [EFLAGS], Predicates = [HasKL] in {
@@ -37,12 +55,8 @@ let SchedRW = [WriteSystem] in {
3755
let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
3856
def ENCODEKEY256 : Encodekey<0xFB, "encodekey256">, T8;
3957

40-
let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [NoEGPR] in {
41-
def AESENC128KL : Aesencdec<0xDC, "aesenc128kl", X86aesenc128kl>, T8;
42-
def AESDEC128KL : Aesencdec<0xDD, "aesdec128kl", X86aesdec128kl>, T8;
43-
def AESENC256KL : Aesencdec<0xDE, "aesenc256kl", X86aesenc256kl>, T8;
44-
def AESDEC256KL : Aesencdec<0xDF, "aesdec256kl", X86aesdec256kl>, T8;
45-
}
58+
let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [NoEGPR] in
59+
defm "" : Aesencdec<"">, T8;
4660
}
4761

4862
let Predicates = [HasKL, HasEGPR, In64BitMode] in {
@@ -52,34 +66,26 @@ let SchedRW = [WriteSystem] in {
5266
let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
5367
def ENCODEKEY256_EVEX : Encodekey<0xDB, "encodekey256">, EVEX, T_MAP4;
5468

55-
let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [HasEGPR, In64BitMode] in {
56-
def AESENC128KL_EVEX : Aesencdec<0xDC, "aesenc128kl", X86aesenc128kl>, EVEX, T_MAP4;
57-
def AESDEC128KL_EVEX : Aesencdec<0xDD, "aesdec128kl", X86aesdec128kl>, EVEX, T_MAP4;
58-
def AESENC256KL_EVEX : Aesencdec<0xDE, "aesenc256kl", X86aesenc256kl>, EVEX, T_MAP4;
59-
def AESDEC256KL_EVEX : Aesencdec<0xDF, "aesdec256kl", X86aesdec256kl>, EVEX, T_MAP4;
60-
}
69+
let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [HasEGPR, In64BitMode] in
70+
defm "" : Aesencdec<"_EVEX">, EVEX, T_MAP4;
6171
}
6272
} // SchedRW
6373

64-
class Aesencdecwide<bits<8> opcode, Format f, string mnemonic>
65-
: I<opcode, f, (outs), (ins opaquemem:$src), mnemonic#"\t$src", []>, NoCD8, XS;
74+
multiclass Aesencdecwide<string suffix> {
75+
def AESENCWIDE128KL#suffix : I<0xD8, MRM0m, (outs), (ins opaquemem:$src), "aesencwide128kl\t$src", []>, NoCD8, XS;
76+
def AESDECWIDE128KL#suffix : I<0xD8, MRM1m, (outs), (ins opaquemem:$src), "aesdecwide128kl\t$src", []>, NoCD8, XS;
77+
def AESENCWIDE256KL#suffix : I<0xD8, MRM2m, (outs), (ins opaquemem:$src), "aesencwide256kl\t$src", []>, NoCD8, XS;
78+
def AESDECWIDE256KL#suffix : I<0xD8, MRM3m, (outs), (ins opaquemem:$src), "aesdecwide256kl\t$src", []>, NoCD8, XS;
79+
}
6680

6781
let SchedRW = [WriteSystem] in {
6882
let Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
6983
Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
7084
mayLoad = 1 in {
71-
let Predicates = [HasWIDEKL, NoEGPR] in {
72-
def AESENCWIDE128KL : Aesencdecwide<0xD8, MRM0m, "aesencwide128kl">, T8;
73-
def AESDECWIDE128KL : Aesencdecwide<0xD8, MRM1m, "aesdecwide128kl">, T8;
74-
def AESENCWIDE256KL : Aesencdecwide<0xD8, MRM2m, "aesencwide256kl">, T8;
75-
def AESDECWIDE256KL : Aesencdecwide<0xD8, MRM3m, "aesdecwide256kl">, T8;
76-
}
85+
let Predicates = [HasWIDEKL, NoEGPR] in
86+
defm "" : Aesencdecwide<"">, T8;
7787

78-
let Predicates = [HasWIDEKL, HasEGPR, In64BitMode] in {
79-
def AESENCWIDE128KL_EVEX : Aesencdecwide<0xD8, MRM0m, "aesencwide128kl">, EVEX, T_MAP4;
80-
def AESDECWIDE128KL_EVEX : Aesencdecwide<0xD8, MRM1m, "aesdecwide128kl">, EVEX, T_MAP4;
81-
def AESENCWIDE256KL_EVEX : Aesencdecwide<0xD8, MRM2m, "aesencwide256kl">, EVEX, T_MAP4;
82-
def AESDECWIDE256KL_EVEX : Aesencdecwide<0xD8, MRM3m, "aesdecwide256kl">, EVEX, T_MAP4;
83-
}
88+
let Predicates = [HasWIDEKL, HasEGPR, In64BitMode] in
89+
defm "" : Aesencdecwide<"_EVEX">, EVEX, T_MAP4;
8490
}
85-
} // SchedRW, Predicates
91+
} // SchedRW

‎llvm/lib/Target/X86/X86InstrMisc.td

Lines changed: 30 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -1557,52 +1557,40 @@ def MOVDIR64B64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$
15571557
//===----------------------------------------------------------------------===//
15581558
// ENQCMD/S - Enqueue 64-byte command as user with 64-byte write atomicity
15591559
//
1560+
multiclass Enqcmds<string suffix> {
1561+
def ENQCMD32#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
1562+
"enqcmd\t{$src, $dst|$dst, $src}",
1563+
[(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>,
1564+
NoCD8, XD, AdSize32, Requires<[HasENQCMD, NoEGPR]>;
1565+
def ENQCMD64#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
1566+
"enqcmd\t{$src, $dst|$dst, $src}",
1567+
[(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
1568+
NoCD8, XD, AdSize64, Requires<[HasENQCMD, NoEGPR, In64BitMode]>;
1569+
1570+
def ENQCMDS32#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
1571+
"enqcmds\t{$src, $dst|$dst, $src}",
1572+
[(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>,
1573+
NoCD8, XS, AdSize32, Requires<[HasENQCMD, NoEGPR]>;
1574+
def ENQCMDS64#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
1575+
"enqcmds\t{$src, $dst|$dst, $src}",
1576+
[(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
1577+
NoCD8, XS, AdSize64, Requires<[HasENQCMD, NoEGPR, In64BitMode]>;
1578+
}
1579+
15601580
let SchedRW = [WriteStore], Defs = [EFLAGS] in {
15611581
def ENQCMD16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src),
1562-
"enqcmd\t{$src, $dst|$dst, $src}",
1563-
[(set EFLAGS, (X86enqcmd GR16:$dst, addr:$src))]>,
1582+
"enqcmd\t{$src, $dst|$dst, $src}",
1583+
[(set EFLAGS, (X86enqcmd GR16:$dst, addr:$src))]>,
15641584
T8, XD, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
1565-
def ENQCMD32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
1566-
"enqcmd\t{$src, $dst|$dst, $src}",
1567-
[(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>,
1568-
T8, XD, AdSize32, Requires<[HasENQCMD]>;
1569-
def ENQCMD64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
1570-
"enqcmd\t{$src, $dst|$dst, $src}",
1571-
[(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
1572-
T8, XD, AdSize64, Requires<[HasENQCMD, NoEGPR, In64BitMode]>;
1573-
15741585
def ENQCMDS16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src),
1575-
"enqcmds\t{$src, $dst|$dst, $src}",
1576-
[(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>,
1577-
T8, XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
1578-
def ENQCMDS32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
1579-
"enqcmds\t{$src, $dst|$dst, $src}",
1580-
[(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>,
1581-
T8, XS, AdSize32, Requires<[HasENQCMD]>;
1582-
def ENQCMDS64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
1583-
"enqcmds\t{$src, $dst|$dst, $src}",
1584-
[(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
1585-
T8, XS, AdSize64, Requires<[HasENQCMD, NoEGPR, In64BitMode]>;
1586-
1587-
let Predicates = [HasENQCMD, HasEGPR, In64BitMode] in {
1588-
def ENQCMD32_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
1589-
"enqcmd\t{$src, $dst|$dst, $src}",
1590-
[(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>,
1591-
EVEX, NoCD8, T_MAP4, XD, AdSize32;
1592-
def ENQCMD64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
1593-
"enqcmd\t{$src, $dst|$dst, $src}",
1594-
[(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
1595-
EVEX, NoCD8, T_MAP4, XD, AdSize64;
1596-
1597-
def ENQCMDS32_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
1598-
"enqcmds\t{$src, $dst|$dst, $src}",
1599-
[(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>,
1600-
EVEX, NoCD8, T_MAP4, XS, AdSize32;
1601-
def ENQCMDS64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
1602-
"enqcmds\t{$src, $dst|$dst, $src}",
1603-
[(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
1604-
EVEX, NoCD8, T_MAP4, XS, AdSize64;
1605-
}
1586+
"enqcmds\t{$src, $dst|$dst, $src}",
1587+
[(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>,
1588+
T8, XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
1589+
1590+
defm "" : Enqcmds<"">, T8;
1591+
let Predicates = [HasENQCMD, HasEGPR, In64BitMode] in
1592+
defm "" : Enqcmds<"_EVEX">, EVEX, T_MAP4;
1593+
16061594
}
16071595

16081596
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/X86/X86InstrSystem.td

Lines changed: 29 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -436,37 +436,38 @@ def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, TB, XS;
436436
def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, TB, XD;
437437
}
438438

439-
let Predicates = [HasUSERMSR, NoEGPR], mayLoad = 1 in {
440-
def URDMSRrr : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
441-
"urdmsr\t{$src, $dst|$dst, $src}",
442-
[(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, T8, XD;
443-
def URDMSRri : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
444-
"urdmsr\t{$imm, $dst|$dst, $imm}",
445-
[(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>, T_MAP7, XD, VEX;
439+
multiclass Urdwrmsr_rr<string suffix> {
440+
let mayLoad = 1 in
441+
def URDMSRrr#suffix : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
442+
"urdmsr\t{$src, $dst|$dst, $src}",
443+
[(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, XD, NoCD8;
444+
let mayStore = 1 in
445+
def UWRMSRrr#suffix : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
446+
"uwrmsr\t{$src2, $src1|$src1, $src2}",
447+
[(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, XS, NoCD8;
446448
}
447-
let Predicates = [HasUSERMSR, NoEGPR], mayStore = 1 in {
448-
def UWRMSRrr : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
449-
"uwrmsr\t{$src2, $src1|$src1, $src2}",
450-
[(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, T8, XS;
451-
def UWRMSRir : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
452-
"uwrmsr\t{$src, $imm|$imm, $src}",
453-
[(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>, T_MAP7, XS, VEX;
449+
450+
multiclass Urdwrmsr_ri<string suffix> {
451+
let mayLoad = 1 in
452+
def URDMSRri#suffix : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
453+
"urdmsr\t{$imm, $dst|$dst, $imm}",
454+
[(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>,
455+
T_MAP7, XD, NoCD8;
456+
let mayStore = 1 in
457+
def UWRMSRir#suffix : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
458+
"uwrmsr\t{$src, $imm|$imm, $src}",
459+
[(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>,
460+
T_MAP7, XS, NoCD8;
454461
}
455-
let Predicates = [HasUSERMSR, HasEGPR, In64BitMode], mayLoad = 1 in {
456-
def URDMSRrr_EVEX : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
457-
"urdmsr\t{$src, $dst|$dst, $src}",
458-
[(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, T_MAP4, XD, EVEX, NoCD8;
459-
def URDMSRri_EVEX : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
460-
"urdmsr\t{$imm, $dst|$dst, $imm}",
461-
[(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>, T_MAP7, XD, EVEX, NoCD8;
462+
463+
let Predicates = [HasUSERMSR, NoEGPR] in {
464+
defm "" : Urdwrmsr_rr<"">, T8;
465+
defm "" : Urdwrmsr_ri<"">, VEX;
462466
}
463-
let Predicates = [HasUSERMSR, HasEGPR, In64BitMode], mayStore = 1 in {
464-
def UWRMSRrr_EVEX : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
465-
"uwrmsr\t{$src2, $src1|$src1, $src2}",
466-
[(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, T_MAP4, XS, EVEX, NoCD8;
467-
def UWRMSRir_EVEX : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
468-
"uwrmsr\t{$src, $imm|$imm, $src}",
469-
[(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>, T_MAP7, XS, EVEX, NoCD8;
467+
468+
let Predicates = [HasUSERMSR, HasEGPR, In64BitMode], mayLoad = 1 in {
469+
defm "" : Urdwrmsr_rr<"_EVEX">, EVEX, T_MAP4;
470+
defm "" : Urdwrmsr_ri<"_EVEX">, EVEX;
470471
}
471472
let Defs = [RAX, RDX], Uses = [ECX] in
472473
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;

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