Precompute subreg info with TableGen

Author: sdesmalen-arm

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

@@ -745,6 +745,15 @@ class TargetRegisterInfo : public MCRegisterInfo {
     return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
   }
 
+  /// Returns the number of allocatable sub registers for R, which is the
+  /// number of register units that are not artificial and part of an
+  /// allocatable register class. For a register like D0_D1, which consists of
+  /// D0 and D1, this function would return '2'. For an architecture where
+  /// D0=S0_S1 and D1=S2_S3, this would return '4' for S0, S1, S2, S3.
+  unsigned getNumAllocatableSubRegs(MCPhysReg R) const {
+    return getNumAllocatableSubRegsImpl(R);
+  }
+
   /// Debugging helper: dump register in human readable form to dbgs() stream.
   static void dumpReg(Register Reg, unsigned SubRegIndex = 0,
                       const TargetRegisterInfo *TRI = nullptr);
@@ -774,6 +783,10 @@ class TargetRegisterInfo : public MCRegisterInfo {
     llvm_unreachable("Target has no sub-registers");
   }
 
+  virtual unsigned getNumAllocatableSubRegsImpl(MCPhysReg) const {
+    llvm_unreachable("Target has no sub-registers");
+  }
+
   /// Return the register cost table index. This implementation is sufficient
   /// for most architectures and can be overriden by targets in case there are
   /// multiple cost values associated with each register.

llvm/lib/CodeGen/LiveIntervals.cpp

@@ -710,30 +710,6 @@ void LiveIntervals::pruneValue(LiveRange &LR, SlotIndex Kill,
 // Register allocator hooks.
 //
 
-/// Returns true if the physreg has multiple regunits that can be accessed
-/// as independent registers.
-///
-/// Returns 'true' for e.g.:
-///   gpr64_0_gpr64_1
-//               => two independently accessible registers gpr64_0 and gpr64_1.
-///
-/// Returns 'false' for e.g.:
-///   gpr64_0:   => accessible register, reads/writes 64bits
-///   gpr32_0:   => accessible sub-regsiter of gpr64_0, reads/writes 32bits
-//    gpr32_0_hi => top 32bits of gpr64_0, not independently accessible.
-static bool hasMultipleAddressableRegUnits(const TargetRegisterInfo *TRI,
-                                           MCPhysReg PhysReg) {
-  unsigned NumAddressableRegUnits = 0;
-  for (MCRegUnit U : TRI->regunits(PhysReg)) {
-    for (MCRegUnitRootIterator RI(U, TRI); RI.isValid(); ++RI)
-      if (!TRI->isArtificial(*RI) && TRI->isInAllocatableClass(*RI))
-        NumAddressableRegUnits++;
-    if (NumAddressableRegUnits > 1)
-      return true;
-  }
-  return false;
-}
-
 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
   // Keep track of regunit ranges.
   SmallVector<std::pair<const LiveRange*, LiveRange::const_iterator>, 8> RU;
@@ -760,18 +736,6 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
         continue;
       RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));
     }
-
-    // If parts of a physical register for a given liverange, as assigned by the
-    // register allocator, can be used to store other values not represented by
-    // this liverange, then `LiveIntervals::addKillFlags` normally avoids adding
-    // a kill flag on the use of this register when the value's liverange ends.
-    //
-    // However, if all the other regunits are artificial, then we can still
-    // safely add the kill flag, since those parts of the register can never be
-    // accessed independently.
-    bool AssumeOtherUnitsCanBeUsed =
-        hasMultipleAddressableRegUnits(TRI, PhysReg);
-
     // Every instruction that kills Reg corresponds to a segment range end
     // point.
     for (LiveInterval::const_iterator RI = LI.begin(), RE = LI.end(); RI != RE;
@@ -806,6 +770,9 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
       if (MRI->subRegLivenessEnabled()) {
         // When reading a partial undefined value we must not add a kill flag.
         // The regalloc might have used the undef lane for something else.
+        // If the register consists of a single allocatable subreg, then
+        // we can assume the other (undef) lanes cannot be used.
+        //
         // Example:
         //     %1 = ...                  ; R32: %1
         //     %2:high16 = ...           ; R64: %2
@@ -816,7 +783,7 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
         // are actually never written by %2. After assignment the <kill>
         // flag at the read instruction is invalid.
         LaneBitmask DefinedLanesMask;
-        if (LI.hasSubRanges() && AssumeOtherUnitsCanBeUsed) {
+        if (LI.hasSubRanges() && TRI->getNumAllocatableSubRegs(PhysReg) > 1) {
           // Compute a mask of lanes that are defined.
           DefinedLanesMask = LaneBitmask::getNone();
           for (const LiveInterval::SubRange &SR : LI.subranges())

llvm/utils/TableGen/RegisterInfoEmitter.cpp

@@ -93,6 +93,8 @@ class RegisterInfoEmitter {
   void EmitRegUnitPressure(raw_ostream &OS, StringRef ClassName);
   void emitComposeSubRegIndices(raw_ostream &OS, StringRef ClassName);
   void emitComposeSubRegIndexLaneMask(raw_ostream &OS, StringRef ClassName);
+  void emitNumAllocatableSubRegs(raw_ostream &OS, StringRef ClassName,
+                                 llvm::BitVector &InAllocClass);
 };
 
 } // end anonymous namespace
@@ -677,6 +679,31 @@ static bool combine(const CodeGenSubRegIndex *Idx,
   return true;
 }
 
+void RegisterInfoEmitter::emitNumAllocatableSubRegs(
+    raw_ostream &OS, StringRef ClassName, llvm::BitVector &InAllocClass) {
+  OS << "unsigned " << ClassName
+     << "::getNumAllocatableSubRegsImpl(MCPhysReg R) const {\n";
+  OS << "  static unsigned numAllocatableSubRegsMap[] = { \n";
+  OS << "    0, // NoRegister\n";
+  const auto &Regs = RegBank.getRegisters();
+  for (auto [I, R] : llvm::enumerate(Regs)) {
+    unsigned NumAllocatableSubRegs = 0;
+    for (unsigned U : R.getRegUnits()) {
+      for (const CodeGenRegister *UR : RegBank.getRegUnit(U).getRoots())
+        if (!UR->Artificial && InAllocClass[UR->EnumValue])
+          NumAllocatableSubRegs++;
+    }
+    OS << "    " << NumAllocatableSubRegs;
+    if (I < Regs.size() - 1)
+      OS << ",";
+    OS << " // " << R.getName() << "\n";
+  }
+  OS << "  };\n";
+  OS << "  assert(R <= " << Regs.size() << " && \"Unexpected physreg\");\n";
+  OS << "  return numAllocatableSubRegsMap[R];\n";
+  OS << "};\n";
+}
+
 void RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
                                                    StringRef ClassName) {
   const auto &SubRegIndices = RegBank.getSubRegIndices();
@@ -1122,7 +1149,9 @@ void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS) {
        << "  const TargetRegisterClass *getSubClassWithSubReg"
        << "(const TargetRegisterClass *, unsigned) const override;\n"
        << "  const TargetRegisterClass *getSubRegisterClass"
-       << "(const TargetRegisterClass *, unsigned) const override;\n";
+       << "(const TargetRegisterClass *, unsigned) const override;\n"
+       << "  unsigned getNumAllocatableSubRegsImpl(MCPhysReg) const "
+          "override;\n";
   }
   OS << "  const RegClassWeight &getRegClassWeight("
      << "const TargetRegisterClass *RC) const override;\n"
@@ -1483,6 +1512,7 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) {
   if (!SubRegIndices.empty()) {
     emitComposeSubRegIndices(OS, ClassName);
     emitComposeSubRegIndexLaneMask(OS, ClassName);
+    emitNumAllocatableSubRegs(OS, ClassName, InAllocClass);
   }
 
   if (!SubRegIndices.empty()) {