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[AMDGPU][NFC] Make GFX*Gen records globally available. (#97291)
And use them to simplify SOP-related definitions. Introduces GFX10Gen.
1 parent 99d8bc9 commit 47c3eca

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-54
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3 files changed

+43
-54
lines changed

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,21 @@ def SIEncodingFamily {
3333
int GFX12 = 11;
3434
}
3535

36+
//===----------------------------------------------------------------------===//
37+
// Subtarget info
38+
//===----------------------------------------------------------------------===//
39+
40+
class GFXGen<Predicate pred, string dn, string suffix, int sub> {
41+
Predicate AssemblerPredicate = pred;
42+
string DecoderNamespace = dn;
43+
string Suffix = suffix;
44+
int Subtarget = sub;
45+
}
46+
47+
def GFX12Gen : GFXGen<isGFX12Only, "GFX12", "_gfx12", SIEncodingFamily.GFX12>;
48+
def GFX11Gen : GFXGen<isGFX11Only, "GFX11", "_gfx11", SIEncodingFamily.GFX11>;
49+
def GFX10Gen : GFXGen<isGFX10Only, "GFX10", "_gfx10", SIEncodingFamily.GFX10>;
50+
3651
//===----------------------------------------------------------------------===//
3752
// SI DAG Nodes
3853
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/SOPInstructions.td

Lines changed: 28 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -1966,19 +1966,9 @@ def : ScalarNot2Pat<S_ORN2_B64, or, v2i32>;
19661966
// Target-specific instruction encodings.
19671967
//===----------------------------------------------------------------------===//
19681968

1969-
class Select_gfx12<string opName> : SIMCInstr<opName, SIEncodingFamily.GFX12> {
1970-
Predicate AssemblerPredicate = isGFX12Only;
1971-
string DecoderNamespace = "GFX12";
1972-
}
1973-
1974-
class Select_gfx11<string opName> : SIMCInstr<opName, SIEncodingFamily.GFX11> {
1975-
Predicate AssemblerPredicate = isGFX11Only;
1976-
string DecoderNamespace = "GFX11";
1977-
}
1978-
1979-
class Select_gfx10<string opName> : SIMCInstr<opName, SIEncodingFamily.GFX10> {
1980-
Predicate AssemblerPredicate = isGFX10Only;
1981-
string DecoderNamespace = "GFX10";
1969+
class Select<GFXGen Gen, string opName> : SIMCInstr<opName, Gen.Subtarget> {
1970+
Predicate AssemblerPredicate = Gen.AssemblerPredicate;
1971+
string DecoderNamespace = Gen.DecoderNamespace;
19821972
}
19831973

19841974
class Select_vi<string opName> : SIMCInstr<opName, SIEncodingFamily.VI> {
@@ -1998,7 +1988,7 @@ class Select_gfx6_gfx7<string opName> : SIMCInstr<opName, SIEncodingFamily.SI> {
19981988
multiclass SOP1_Real_gfx11<bits<8> op, string name = !tolower(NAME)> {
19991989
defvar ps = !cast<SOP1_Pseudo>(NAME);
20001990
def _gfx11 : SOP1_Real<op, ps, name>,
2001-
Select_gfx11<ps.PseudoInstr>;
1991+
Select<GFX11Gen, ps.PseudoInstr>;
20021992
if !ne(ps.Mnemonic, name) then
20031993
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
20041994
let AssemblerPredicate = isGFX11Only;
@@ -2008,7 +1998,7 @@ multiclass SOP1_Real_gfx11<bits<8> op, string name = !tolower(NAME)> {
20081998
multiclass SOP1_Real_gfx12<bits<8> op, string name = !tolower(NAME)> {
20091999
defvar ps = !cast<SOP1_Pseudo>(NAME);
20102000
def _gfx12 : SOP1_Real<op, ps, name>,
2011-
Select_gfx12<ps.PseudoInstr>;
2001+
Select<GFX12Gen, ps.PseudoInstr>;
20122002
if !ne(ps.Mnemonic, name) then
20132003
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
20142004
let AssemblerPredicate = isGFX12Plus;
@@ -2017,15 +2007,15 @@ multiclass SOP1_Real_gfx12<bits<8> op, string name = !tolower(NAME)> {
20172007

20182008
multiclass SOP1_M0_Real_gfx12<bits<8> op> {
20192009
def _gfx12 : SOP1_Real<op, !cast<SOP1_Pseudo>(NAME)>,
2020-
Select_gfx12<!cast<SOP1_Pseudo>(NAME).PseudoInstr> {
2010+
Select<GFX12Gen, !cast<SOP1_Pseudo>(NAME).PseudoInstr> {
20212011
let Inst{7-0} = M0_gfx11plus.HWEncoding{7-0}; // Set Src0 encoding to M0
20222012
}
20232013
}
20242014

20252015
multiclass SOP1_IMM_Real_gfx12<bits<8> op> {
20262016
defvar ps = !cast<SOP1_Pseudo>(NAME);
20272017
def _gfx12 : SOP1_Real<op, ps>,
2028-
Select_gfx12<ps.PseudoInstr>;
2018+
Select<GFX12Gen, ps.PseudoInstr>;
20292019
}
20302020

20312021
multiclass SOP1_Real_gfx11_gfx12<bits<8> op, string name = !tolower(NAME)> :
@@ -2136,7 +2126,7 @@ defm S_RNDNE_F16 : SOP1_Real_gfx11_gfx12<0x06e>;
21362126
multiclass SOP1_Real_gfx10<bits<8> op> {
21372127
defvar ps = !cast<SOP1_Pseudo>(NAME);
21382128
def _gfx10 : SOP1_Real<op, ps>,
2139-
Select_gfx10<ps.PseudoInstr>;
2129+
Select<GFX10Gen, ps.PseudoInstr>;
21402130
}
21412131

21422132
multiclass SOP1_Real_gfx10_gfx11_gfx12<bits<8> op> :
@@ -2235,7 +2225,7 @@ defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x034>;
22352225
multiclass SOP2_Real_gfx12<bits<7> op, string name = !tolower(NAME)> {
22362226
defvar ps = !cast<SOP2_Pseudo>(NAME);
22372227
def _gfx12 : SOP2_Real32<op, ps, name>,
2238-
Select_gfx12<ps.PseudoInstr>;
2228+
Select<GFX12Gen, ps.PseudoInstr>;
22392229
if !ne(ps.Mnemonic, name) then
22402230
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
22412231
let AssemblerPredicate = isGFX12Plus;
@@ -2254,7 +2244,7 @@ defm S_MAXIMUM_F16 : SOP2_Real_gfx12<0x052>;
22542244
multiclass SOP2_Real_gfx11<bits<7> op, string name = !tolower(NAME)> {
22552245
defvar ps = !cast<SOP2_Pseudo>(NAME);
22562246
def _gfx11 : SOP2_Real32<op, ps, name>,
2257-
Select_gfx11<ps.PseudoInstr>;
2247+
Select<GFX11Gen, ps.PseudoInstr>;
22582248
if !ne(ps.Mnemonic, name) then
22592249
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
22602250
let AssemblerPredicate = isGFX11Only;
@@ -2317,12 +2307,12 @@ defm S_MUL_U64 : SOP2_Real_gfx12<0x055>;
23172307

23182308
multiclass SOP2_Real_FMAK_gfx12<bits<7> op> {
23192309
def _gfx12 : SOP2_Real64<op, !cast<SOP2_Pseudo>(NAME)>,
2320-
Select_gfx12<!cast<SOP2_Pseudo>(NAME).PseudoInstr>;
2310+
Select<GFX12Gen, !cast<SOP2_Pseudo>(NAME).PseudoInstr>;
23212311
}
23222312

23232313
multiclass SOP2_Real_FMAK_gfx11<bits<7> op> {
23242314
def _gfx11 : SOP2_Real64<op, !cast<SOP2_Pseudo>(NAME)>,
2325-
Select_gfx11<!cast<SOP2_Pseudo>(NAME).PseudoInstr>;
2315+
Select<GFX11Gen, !cast<SOP2_Pseudo>(NAME).PseudoInstr>;
23262316
}
23272317

23282318
multiclass SOP2_Real_FMAK_gfx11_gfx12<bits<7> op> :
@@ -2359,7 +2349,7 @@ defm S_MAX_F16 : SOP2_Real_gfx11_Renamed_gfx12<0x04c, "s_max_num_f16">;
23592349
multiclass SOP2_Real_gfx10<bits<7> op> {
23602350
defvar ps = !cast<SOP2_Pseudo>(NAME);
23612351
def _gfx10 : SOP2_Real32<op, ps>,
2362-
Select_gfx10<ps.PseudoInstr>;
2352+
Select<GFX10Gen, ps.PseudoInstr>;
23632353
}
23642354

23652355
multiclass SOP2_Real_gfx10_gfx11_gfx12<bits<7> op> :
@@ -2444,7 +2434,7 @@ defm S_ABSDIFF_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x02c>;
24442434
multiclass SOPK_Real32_gfx12<bits<5> op, string name = !tolower(NAME)> {
24452435
defvar ps = !cast<SOPK_Pseudo>(NAME);
24462436
def _gfx12 : SOPK_Real32<op, ps, name>,
2447-
Select_gfx12<ps.PseudoInstr>;
2437+
Select<GFX12Gen, ps.PseudoInstr>;
24482438
if !ne(ps.Mnemonic, name) then
24492439
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
24502440
let AssemblerPredicate = isGFX12Plus;
@@ -2453,17 +2443,17 @@ multiclass SOPK_Real32_gfx12<bits<5> op, string name = !tolower(NAME)> {
24532443

24542444
multiclass SOPK_Real32_gfx11<bits<5> op> {
24552445
def _gfx11 : SOPK_Real32<op, !cast<SOPK_Pseudo>(NAME)>,
2456-
Select_gfx11<!cast<SOPK_Pseudo>(NAME).PseudoInstr>;
2446+
Select<GFX11Gen, !cast<SOPK_Pseudo>(NAME).PseudoInstr>;
24572447
}
24582448

24592449
multiclass SOPK_Real64_gfx12<bits<5> op> {
24602450
def _gfx12 : SOPK_Real64<op, !cast<SOPK_Pseudo>(NAME)>,
2461-
Select_gfx12<!cast<SOPK_Pseudo>(NAME).PseudoInstr>;
2451+
Select<GFX12Gen, !cast<SOPK_Pseudo>(NAME).PseudoInstr>;
24622452
}
24632453

24642454
multiclass SOPK_Real64_gfx11<bits<5> op> {
24652455
def _gfx11 : SOPK_Real64<op, !cast<SOPK_Pseudo>(NAME)>,
2466-
Select_gfx11<!cast<SOPK_Pseudo>(NAME).PseudoInstr>;
2456+
Select<GFX11Gen, !cast<SOPK_Pseudo>(NAME).PseudoInstr>;
24672457
}
24682458

24692459
multiclass SOPK_Real32_gfx11_gfx12<bits<5> op> :
@@ -2490,13 +2480,13 @@ defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx11<0x01b>;
24902480
multiclass SOPK_Real32_gfx10<bits<5> op> {
24912481
defvar ps = !cast<SOPK_Pseudo>(NAME);
24922482
def _gfx10 : SOPK_Real32<op, ps>,
2493-
Select_gfx10<ps.PseudoInstr>;
2483+
Select<GFX10Gen, ps.PseudoInstr>;
24942484
}
24952485

24962486
multiclass SOPK_Real64_gfx10<bits<5> op> {
24972487
defvar ps = !cast<SOPK_Pseudo>(NAME);
24982488
def _gfx10 : SOPK_Real64<op, ps>,
2499-
Select_gfx10<ps.PseudoInstr>;
2489+
Select<GFX10Gen, ps.PseudoInstr>;
25002490
}
25012491

25022492
multiclass SOPK_Real32_gfx10_gfx11<bits<5> op> :
@@ -2575,7 +2565,7 @@ defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>;
25752565
multiclass SOPP_Real_32_gfx12<bits<7> op, string name = !tolower(NAME)> {
25762566
defvar ps = !cast<SOPP_Pseudo>(NAME);
25772567
def _gfx12 : SOPP_Real_32<op, ps, name>,
2578-
Select_gfx12<ps.PseudoInstr>;
2568+
Select<GFX12Gen, ps.PseudoInstr>;
25792569
if !ne(ps.Mnemonic, name) then
25802570
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
25812571
let AssemblerPredicate = isGFX12Plus;
@@ -2602,7 +2592,7 @@ defm S_WAIT_STORECNT_DSCNT : SOPP_Real_32_gfx12<0x049>;
26022592
multiclass SOPP_Real_32_gfx11<bits<7> op, string name = !tolower(NAME)> {
26032593
defvar ps = !cast<SOPP_Pseudo>(NAME);
26042594
def _gfx11 : SOPP_Real_32<op, ps, name>,
2605-
Select_gfx11<ps.PseudoInstr>,
2595+
Select<GFX11Gen, ps.PseudoInstr>,
26062596
SOPPRelaxTable<0, ps.KeyName, "_gfx11">;
26072597
if !ne(ps.Mnemonic, name) then
26082598
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
@@ -2612,13 +2602,13 @@ multiclass SOPP_Real_32_gfx11<bits<7> op, string name = !tolower(NAME)> {
26122602

26132603
multiclass SOPP_Real_64_gfx12<bits<7> op> {
26142604
def _gfx12 : SOPP_Real_64<op, !cast<SOPP_Pseudo>(NAME), !cast<SOPP_Pseudo>(NAME).Mnemonic>,
2615-
Select_gfx12<!cast<SOPP_Pseudo>(NAME).PseudoInstr>,
2605+
Select<GFX12Gen, !cast<SOPP_Pseudo>(NAME).PseudoInstr>,
26162606
SOPPRelaxTable<1, !cast<SOPP_Pseudo>(NAME).KeyName, "_gfx12">;
26172607
}
26182608

26192609
multiclass SOPP_Real_64_gfx11<bits<7> op> {
26202610
def _gfx11 : SOPP_Real_64<op, !cast<SOPP_Pseudo>(NAME), !cast<SOPP_Pseudo>(NAME).Mnemonic>,
2621-
Select_gfx11<!cast<SOPP_Pseudo>(NAME).PseudoInstr>,
2611+
Select<GFX11Gen, !cast<SOPP_Pseudo>(NAME).PseudoInstr>,
26222612
SOPPRelaxTable<1, !cast<SOPP_Pseudo>(NAME).KeyName, "_gfx11">;
26232613
}
26242614

@@ -2708,7 +2698,7 @@ multiclass SOPP_Real_32_gfx8_gfx9<bits<7> op> {
27082698
multiclass SOPP_Real_32_gfx10<bits<7> op> {
27092699
defvar ps = !cast<SOPP_Pseudo>(NAME);
27102700
def _gfx10 : SOPP_Real_32<op, ps>,
2711-
Select_gfx10<ps.PseudoInstr>,
2701+
Select<GFX10Gen, ps.PseudoInstr>,
27122702
SOPPRelaxTable<0, ps.KeyName, "_gfx10">;
27132703
}
27142704

@@ -2745,7 +2735,7 @@ multiclass SOPP_Real_64_gfx8_gfx9<bits<7> op> {
27452735
multiclass SOPP_Real_64_gfx10<bits<7> op> {
27462736
defvar ps = !cast<SOPP_Pseudo>(NAME);
27472737
def _gfx10 : SOPP_Real_64<op, ps>,
2748-
Select_gfx10<ps.PseudoInstr>,
2738+
Select<GFX10Gen, ps.PseudoInstr>,
27492739
SOPPRelaxTable<1, ps.KeyName, "_gfx10">;
27502740
}
27512741

@@ -2811,12 +2801,12 @@ defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_
28112801

28122802
multiclass SOPC_Real_gfx12<bits<7> op> {
28132803
def _gfx12 : SOPC_Real<op, !cast<SOPC_Pseudo>(NAME)>,
2814-
Select_gfx12<!cast<SOPC_Pseudo>(NAME).PseudoInstr>;
2804+
Select<GFX12Gen, !cast<SOPC_Pseudo>(NAME).PseudoInstr>;
28152805
}
28162806

28172807
multiclass SOPC_Real_gfx11<bits<7> op> {
28182808
def _gfx11 : SOPC_Real<op, !cast<SOPC_Pseudo>(NAME)>,
2819-
Select_gfx11<!cast<SOPC_Pseudo>(NAME).PseudoInstr>;
2809+
Select<GFX11Gen, !cast<SOPC_Pseudo>(NAME).PseudoInstr>;
28202810
}
28212811

28222812
multiclass SOPC_Real_gfx11_gfx12<bits<7> op> :
@@ -2878,7 +2868,7 @@ multiclass SOPC_Real_gfx8_gfx9<bits<7> op> {
28782868
multiclass SOPC_Real_gfx10<bits<7> op> {
28792869
defvar ps = !cast<SOPC_Pseudo>(NAME);
28802870
def _gfx10 : SOPC_Real<op, ps>,
2881-
Select_gfx10<ps.PseudoInstr>;
2871+
Select<GFX10Gen, ps.PseudoInstr>;
28822872
}
28832873

28842874
multiclass SOPC_Real_gfx8_gfx9_gfx10<bits<7> op> :

‎llvm/lib/Target/AMDGPU/VOPInstructions.td

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -30,22 +30,6 @@ class LetDummies {
3030
string DecoderNamespace;
3131
}
3232

33-
//===----------------------------------------------------------------------===//
34-
// VOP Subtarget info
35-
//===----------------------------------------------------------------------===//
36-
37-
class GFXGen<Predicate pred, string dn, string suffix, int sub> {
38-
Predicate AssemblerPredicate = pred;
39-
string DecoderNamespace = dn;
40-
string Suffix = suffix;
41-
int Subtarget = sub;
42-
}
43-
44-
def GFX12Gen : GFXGen<isGFX12Only, "GFX12", "_gfx12", SIEncodingFamily.GFX12>;
45-
def GFX11Gen : GFXGen<isGFX11Only, "GFX11", "_gfx11", SIEncodingFamily.GFX11>;
46-
47-
//===----------------------------------------------------------------------===//
48-
4933
class VOP <string opName> {
5034
string OpName = opName;
5135
}

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