[AMDGPU][NFC] Make GFX*Gen records globally available. #97291
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And use them to simplify SOP-related definitions. Introduces GFX10Gen.
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@llvm/pr-subscribers-backend-amdgpu Author: Ivan Kosarev (kosarev) ChangesAnd use them to simplify SOP-related definitions. Introduces GFX10Gen. Full diff: https://github.com/llvm/llvm-project/pull/97291.diff 3 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index c64b3a7c356f2..d2838349340d2 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -33,6 +33,21 @@ def SIEncodingFamily {
int GFX12 = 11;
}
+//===----------------------------------------------------------------------===//
+// Subtarget info
+//===----------------------------------------------------------------------===//
+
+class GFXGen<Predicate pred, string dn, string suffix, int sub> {
+ Predicate AssemblerPredicate = pred;
+ string DecoderNamespace = dn;
+ string Suffix = suffix;
+ int Subtarget = sub;
+}
+
+def GFX12Gen : GFXGen<isGFX12Only, "GFX12", "_gfx12", SIEncodingFamily.GFX12>;
+def GFX11Gen : GFXGen<isGFX11Only, "GFX11", "_gfx11", SIEncodingFamily.GFX11>;
+def GFX10Gen : GFXGen<isGFX10Only, "GFX10", "_gfx10", SIEncodingFamily.GFX10>;
+
//===----------------------------------------------------------------------===//
// SI DAG Nodes
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 64f33199545a1..0d6883254c350 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1966,19 +1966,9 @@ def : ScalarNot2Pat<S_ORN2_B64, or, v2i32>;
// Target-specific instruction encodings.
//===----------------------------------------------------------------------===//
-class Select_gfx12<string opName> : SIMCInstr<opName, SIEncodingFamily.GFX12> {
- Predicate AssemblerPredicate = isGFX12Only;
- string DecoderNamespace = "GFX12";
-}
-
-class Select_gfx11<string opName> : SIMCInstr<opName, SIEncodingFamily.GFX11> {
- Predicate AssemblerPredicate = isGFX11Only;
- string DecoderNamespace = "GFX11";
-}
-
-class Select_gfx10<string opName> : SIMCInstr<opName, SIEncodingFamily.GFX10> {
- Predicate AssemblerPredicate = isGFX10Only;
- string DecoderNamespace = "GFX10";
+class Select<GFXGen Gen, string opName> : SIMCInstr<opName, Gen.Subtarget> {
+ Predicate AssemblerPredicate = Gen.AssemblerPredicate;
+ string DecoderNamespace = Gen.DecoderNamespace;
}
class Select_vi<string opName> : SIMCInstr<opName, SIEncodingFamily.VI> {
@@ -1998,7 +1988,7 @@ class Select_gfx6_gfx7<string opName> : SIMCInstr<opName, SIEncodingFamily.SI> {
multiclass SOP1_Real_gfx11<bits<8> op, string name = !tolower(NAME)> {
defvar ps = !cast<SOP1_Pseudo>(NAME);
def _gfx11 : SOP1_Real<op, ps, name>,
- Select_gfx11<ps.PseudoInstr>;
+ Select<GFX11Gen, ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
let AssemblerPredicate = isGFX11Only;
@@ -2008,7 +1998,7 @@ multiclass SOP1_Real_gfx11<bits<8> op, string name = !tolower(NAME)> {
multiclass SOP1_Real_gfx12<bits<8> op, string name = !tolower(NAME)> {
defvar ps = !cast<SOP1_Pseudo>(NAME);
def _gfx12 : SOP1_Real<op, ps, name>,
- Select_gfx12<ps.PseudoInstr>;
+ Select<GFX12Gen, ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
let AssemblerPredicate = isGFX12Plus;
@@ -2017,7 +2007,7 @@ multiclass SOP1_Real_gfx12<bits<8> op, string name = !tolower(NAME)> {
multiclass SOP1_M0_Real_gfx12<bits<8> op> {
def _gfx12 : SOP1_Real<op, !cast<SOP1_Pseudo>(NAME)>,
- Select_gfx12<!cast<SOP1_Pseudo>(NAME).PseudoInstr> {
+ Select<GFX12Gen, !cast<SOP1_Pseudo>(NAME).PseudoInstr> {
let Inst{7-0} = M0_gfx11plus.HWEncoding{7-0}; // Set Src0 encoding to M0
}
}
@@ -2025,7 +2015,7 @@ multiclass SOP1_M0_Real_gfx12<bits<8> op> {
multiclass SOP1_IMM_Real_gfx12<bits<8> op> {
defvar ps = !cast<SOP1_Pseudo>(NAME);
def _gfx12 : SOP1_Real<op, ps>,
- Select_gfx12<ps.PseudoInstr>;
+ Select<GFX12Gen, ps.PseudoInstr>;
}
multiclass SOP1_Real_gfx11_gfx12<bits<8> op, string name = !tolower(NAME)> :
@@ -2136,7 +2126,7 @@ defm S_RNDNE_F16 : SOP1_Real_gfx11_gfx12<0x06e>;
multiclass SOP1_Real_gfx10<bits<8> op> {
defvar ps = !cast<SOP1_Pseudo>(NAME);
def _gfx10 : SOP1_Real<op, ps>,
- Select_gfx10<ps.PseudoInstr>;
+ Select<GFX10Gen, ps.PseudoInstr>;
}
multiclass SOP1_Real_gfx10_gfx11_gfx12<bits<8> op> :
@@ -2235,7 +2225,7 @@ defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x034>;
multiclass SOP2_Real_gfx12<bits<7> op, string name = !tolower(NAME)> {
defvar ps = !cast<SOP2_Pseudo>(NAME);
def _gfx12 : SOP2_Real32<op, ps, name>,
- Select_gfx12<ps.PseudoInstr>;
+ Select<GFX12Gen, ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
let AssemblerPredicate = isGFX12Plus;
@@ -2254,7 +2244,7 @@ defm S_MAXIMUM_F16 : SOP2_Real_gfx12<0x052>;
multiclass SOP2_Real_gfx11<bits<7> op, string name = !tolower(NAME)> {
defvar ps = !cast<SOP2_Pseudo>(NAME);
def _gfx11 : SOP2_Real32<op, ps, name>,
- Select_gfx11<ps.PseudoInstr>;
+ Select<GFX11Gen, ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
let AssemblerPredicate = isGFX11Only;
@@ -2317,12 +2307,12 @@ defm S_MUL_U64 : SOP2_Real_gfx12<0x055>;
multiclass SOP2_Real_FMAK_gfx12<bits<7> op> {
def _gfx12 : SOP2_Real64<op, !cast<SOP2_Pseudo>(NAME)>,
- Select_gfx12<!cast<SOP2_Pseudo>(NAME).PseudoInstr>;
+ Select<GFX12Gen, !cast<SOP2_Pseudo>(NAME).PseudoInstr>;
}
multiclass SOP2_Real_FMAK_gfx11<bits<7> op> {
def _gfx11 : SOP2_Real64<op, !cast<SOP2_Pseudo>(NAME)>,
- Select_gfx11<!cast<SOP2_Pseudo>(NAME).PseudoInstr>;
+ Select<GFX11Gen, !cast<SOP2_Pseudo>(NAME).PseudoInstr>;
}
multiclass SOP2_Real_FMAK_gfx11_gfx12<bits<7> op> :
@@ -2359,7 +2349,7 @@ defm S_MAX_F16 : SOP2_Real_gfx11_Renamed_gfx12<0x04c, "s_max_num_f16">;
multiclass SOP2_Real_gfx10<bits<7> op> {
defvar ps = !cast<SOP2_Pseudo>(NAME);
def _gfx10 : SOP2_Real32<op, ps>,
- Select_gfx10<ps.PseudoInstr>;
+ Select<GFX10Gen, ps.PseudoInstr>;
}
multiclass SOP2_Real_gfx10_gfx11_gfx12<bits<7> op> :
@@ -2444,7 +2434,7 @@ defm S_ABSDIFF_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x02c>;
multiclass SOPK_Real32_gfx12<bits<5> op, string name = !tolower(NAME)> {
defvar ps = !cast<SOPK_Pseudo>(NAME);
def _gfx12 : SOPK_Real32<op, ps, name>,
- Select_gfx12<ps.PseudoInstr>;
+ Select<GFX12Gen, ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
let AssemblerPredicate = isGFX12Plus;
@@ -2453,17 +2443,17 @@ multiclass SOPK_Real32_gfx12<bits<5> op, string name = !tolower(NAME)> {
multiclass SOPK_Real32_gfx11<bits<5> op> {
def _gfx11 : SOPK_Real32<op, !cast<SOPK_Pseudo>(NAME)>,
- Select_gfx11<!cast<SOPK_Pseudo>(NAME).PseudoInstr>;
+ Select<GFX11Gen, !cast<SOPK_Pseudo>(NAME).PseudoInstr>;
}
multiclass SOPK_Real64_gfx12<bits<5> op> {
def _gfx12 : SOPK_Real64<op, !cast<SOPK_Pseudo>(NAME)>,
- Select_gfx12<!cast<SOPK_Pseudo>(NAME).PseudoInstr>;
+ Select<GFX12Gen, !cast<SOPK_Pseudo>(NAME).PseudoInstr>;
}
multiclass SOPK_Real64_gfx11<bits<5> op> {
def _gfx11 : SOPK_Real64<op, !cast<SOPK_Pseudo>(NAME)>,
- Select_gfx11<!cast<SOPK_Pseudo>(NAME).PseudoInstr>;
+ Select<GFX11Gen, !cast<SOPK_Pseudo>(NAME).PseudoInstr>;
}
multiclass SOPK_Real32_gfx11_gfx12<bits<5> op> :
@@ -2490,13 +2480,13 @@ defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx11<0x01b>;
multiclass SOPK_Real32_gfx10<bits<5> op> {
defvar ps = !cast<SOPK_Pseudo>(NAME);
def _gfx10 : SOPK_Real32<op, ps>,
- Select_gfx10<ps.PseudoInstr>;
+ Select<GFX10Gen, ps.PseudoInstr>;
}
multiclass SOPK_Real64_gfx10<bits<5> op> {
defvar ps = !cast<SOPK_Pseudo>(NAME);
def _gfx10 : SOPK_Real64<op, ps>,
- Select_gfx10<ps.PseudoInstr>;
+ Select<GFX10Gen, ps.PseudoInstr>;
}
multiclass SOPK_Real32_gfx10_gfx11<bits<5> op> :
@@ -2575,7 +2565,7 @@ defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>;
multiclass SOPP_Real_32_gfx12<bits<7> op, string name = !tolower(NAME)> {
defvar ps = !cast<SOPP_Pseudo>(NAME);
def _gfx12 : SOPP_Real_32<op, ps, name>,
- Select_gfx12<ps.PseudoInstr>;
+ Select<GFX12Gen, ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
let AssemblerPredicate = isGFX12Plus;
@@ -2602,7 +2592,7 @@ defm S_WAIT_STORECNT_DSCNT : SOPP_Real_32_gfx12<0x049>;
multiclass SOPP_Real_32_gfx11<bits<7> op, string name = !tolower(NAME)> {
defvar ps = !cast<SOPP_Pseudo>(NAME);
def _gfx11 : SOPP_Real_32<op, ps, name>,
- Select_gfx11<ps.PseudoInstr>,
+ Select<GFX11Gen, ps.PseudoInstr>,
SOPPRelaxTable<0, ps.KeyName, "_gfx11">;
if !ne(ps.Mnemonic, name) then
def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {
@@ -2612,13 +2602,13 @@ multiclass SOPP_Real_32_gfx11<bits<7> op, string name = !tolower(NAME)> {
multiclass SOPP_Real_64_gfx12<bits<7> op> {
def _gfx12 : SOPP_Real_64<op, !cast<SOPP_Pseudo>(NAME), !cast<SOPP_Pseudo>(NAME).Mnemonic>,
- Select_gfx12<!cast<SOPP_Pseudo>(NAME).PseudoInstr>,
+ Select<GFX12Gen, !cast<SOPP_Pseudo>(NAME).PseudoInstr>,
SOPPRelaxTable<1, !cast<SOPP_Pseudo>(NAME).KeyName, "_gfx12">;
}
multiclass SOPP_Real_64_gfx11<bits<7> op> {
def _gfx11 : SOPP_Real_64<op, !cast<SOPP_Pseudo>(NAME), !cast<SOPP_Pseudo>(NAME).Mnemonic>,
- Select_gfx11<!cast<SOPP_Pseudo>(NAME).PseudoInstr>,
+ Select<GFX11Gen, !cast<SOPP_Pseudo>(NAME).PseudoInstr>,
SOPPRelaxTable<1, !cast<SOPP_Pseudo>(NAME).KeyName, "_gfx11">;
}
@@ -2708,7 +2698,7 @@ multiclass SOPP_Real_32_gfx8_gfx9<bits<7> op> {
multiclass SOPP_Real_32_gfx10<bits<7> op> {
defvar ps = !cast<SOPP_Pseudo>(NAME);
def _gfx10 : SOPP_Real_32<op, ps>,
- Select_gfx10<ps.PseudoInstr>,
+ Select<GFX10Gen, ps.PseudoInstr>,
SOPPRelaxTable<0, ps.KeyName, "_gfx10">;
}
@@ -2745,7 +2735,7 @@ multiclass SOPP_Real_64_gfx8_gfx9<bits<7> op> {
multiclass SOPP_Real_64_gfx10<bits<7> op> {
defvar ps = !cast<SOPP_Pseudo>(NAME);
def _gfx10 : SOPP_Real_64<op, ps>,
- Select_gfx10<ps.PseudoInstr>,
+ Select<GFX10Gen, ps.PseudoInstr>,
SOPPRelaxTable<1, ps.KeyName, "_gfx10">;
}
@@ -2811,12 +2801,12 @@ defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_
multiclass SOPC_Real_gfx12<bits<7> op> {
def _gfx12 : SOPC_Real<op, !cast<SOPC_Pseudo>(NAME)>,
- Select_gfx12<!cast<SOPC_Pseudo>(NAME).PseudoInstr>;
+ Select<GFX12Gen, !cast<SOPC_Pseudo>(NAME).PseudoInstr>;
}
multiclass SOPC_Real_gfx11<bits<7> op> {
def _gfx11 : SOPC_Real<op, !cast<SOPC_Pseudo>(NAME)>,
- Select_gfx11<!cast<SOPC_Pseudo>(NAME).PseudoInstr>;
+ Select<GFX11Gen, !cast<SOPC_Pseudo>(NAME).PseudoInstr>;
}
multiclass SOPC_Real_gfx11_gfx12<bits<7> op> :
@@ -2878,7 +2868,7 @@ multiclass SOPC_Real_gfx8_gfx9<bits<7> op> {
multiclass SOPC_Real_gfx10<bits<7> op> {
defvar ps = !cast<SOPC_Pseudo>(NAME);
def _gfx10 : SOPC_Real<op, ps>,
- Select_gfx10<ps.PseudoInstr>;
+ Select<GFX10Gen, ps.PseudoInstr>;
}
multiclass SOPC_Real_gfx8_gfx9_gfx10<bits<7> op> :
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index 2b05165cc94bc..f2ed17ac305a1 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -30,22 +30,6 @@ class LetDummies {
string DecoderNamespace;
}
-//===----------------------------------------------------------------------===//
-// VOP Subtarget info
-//===----------------------------------------------------------------------===//
-
-class GFXGen<Predicate pred, string dn, string suffix, int sub> {
- Predicate AssemblerPredicate = pred;
- string DecoderNamespace = dn;
- string Suffix = suffix;
- int Subtarget = sub;
-}
-
-def GFX12Gen : GFXGen<isGFX12Only, "GFX12", "_gfx12", SIEncodingFamily.GFX12>;
-def GFX11Gen : GFXGen<isGFX11Only, "GFX11", "_gfx11", SIEncodingFamily.GFX11>;
-
-//===----------------------------------------------------------------------===//
-
class VOP <string opName> {
string OpName = opName;
}
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arsenm
approved these changes
Jul 1, 2024
lravenclaw
pushed a commit
to lravenclaw/llvm-project
that referenced
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Jul 3, 2024
And use them to simplify SOP-related definitions. Introduces GFX10Gen.
kbluck
pushed a commit
to kbluck/llvm-project
that referenced
this pull request
Jul 6, 2024
And use them to simplify SOP-related definitions. Introduces GFX10Gen.
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And use them to simplify SOP-related definitions.
Introduces GFX10Gen.