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Added test.
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‎llvm/lib/Target/RISCV/RISCVProcessors.td

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@@ -254,7 +254,7 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
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FeatureStdExtZicbop,
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FeatureStdExtZicboz,
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FeatureVendorXVentanaCondOps],
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[TuneVentanaVeyron]>;
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[TuneVeyronFusions]>;
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def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
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NoSchedModel,

‎llvm/test/CodeGen/RISCV/macro-fusions-veyron-v1.mir

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# REQUIRES: asserts
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# RUN: llc -mtriple=riscv64-linux-gnu -mcpu=veyron-v1 -x=mir < %s \
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# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \
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# RUN: -mattr=+lui-addi-fusion,+auipc-addi-fusion,+slli-srli-fusion,+ld-add-fusion \
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# RUN: | FileCheck %s
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# CHECK: lui_addi:%bb.0
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# CHECK: Macro fuse: {{.*}}LUI - ADDI
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---
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name: lui_addi
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10
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%1:gpr = COPY $x10
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%2:gpr = LUI 1
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%3:gpr = ADDI %1, 2
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%4:gpr = ADDI %2, 3
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$x10 = COPY %3
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$x11 = COPY %4
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PseudoRET
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...
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# CHECK: auipc_addi
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# CHECK: Macro fuse: {{.*}}AUIPC - ADDI
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---
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name: auipc_addi
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10
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%1:gpr = COPY $x10
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%2:gpr = AUIPC 1
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%3:gpr = ADDI %1, 2
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%4:gpr = ADDI %2, 3
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$x10 = COPY %3
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$x11 = COPY %4
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PseudoRET
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...
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# CHECK: slli_srli
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# CHECK: Macro fuse: {{.*}}SLLI - SRLI
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---
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name: slli_srli
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10
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%1:gpr = COPY $x10
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%2:gpr = SLLI %1, 32
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%3:gpr = ADDI %1, 3
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%4:gpr = SRLI %2, 4
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$x10 = COPY %3
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$x11 = COPY %4
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PseudoRET
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...
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# CHECK: slli_srli_48
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# CHECK: Macro fuse: {{.*}}SLLI - SRLI
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---
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name: slli_srli_48
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10
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%1:gpr = COPY $x10
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%2:gpr = SLLI %1, 48
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%3:gpr = ADDI %1, 3
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%4:gpr = SRLI %2, 48
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$x10 = COPY %3
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$x11 = COPY %4
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PseudoRET
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...
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# CHECK: slli_srli_no_fusion_0
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# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLI
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---
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name: slli_srli_no_fusion_0
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10
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%1:gpr = COPY $x10
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%2:gpr = SLLI %1, 32
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%3:gpr = ADDI %1, 3
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%4:gpr = SRLI %2, 33
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$x10 = COPY %3
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$x11 = COPY %4
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PseudoRET
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...
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# CHECK: slli_srli_no_fusion_1
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# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLI
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---
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name: slli_srli_no_fusion_1
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10
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%1:gpr = COPY $x10
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%2:gpr = SLLI %1, 48
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%3:gpr = ADDI %1, 3
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%4:gpr = SRLI %2, 4
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$x10 = COPY %3
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$x11 = COPY %4
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PseudoRET
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...
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# CHECK: slli_srli_no_fusion_2
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# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLI
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---
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name: slli_srli_no_fusion_2
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10
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%1:gpr = COPY $x10
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%2:gpr = SLLI %1, 31
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%3:gpr = ADDI %1, 3
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%4:gpr = SRLI %2, 4
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$x10 = COPY %3
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$x11 = COPY %4
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PseudoRET
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...
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# CHECK: slli_srli_no_fusion_3
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# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLI
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---
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name: slli_srli_no_fusion_3
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10
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%1:gpr = COPY $x10
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%2:gpr = SLLI %1, 31
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%3:gpr = ADDI %1, 3
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%4:gpr = SRLI %2, 48
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$x10 = COPY %3
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$x11 = COPY %4
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PseudoRET
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...
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# CHECK: ld_add
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# CHECK: Macro fuse: {{.*}}ADD - LD
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---
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name: ld_add
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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%1:gpr = COPY $x10
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%2:gpr = COPY $x11
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%3:gpr = ADD %1, %2
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%4:gpr = ADDI %2, 3
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%5:gpr = LD %3, 0
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$x10 = COPY %4
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$x11 = COPY %5
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PseudoRET
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...

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