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AMDGPU: Fix foldImmediate breaking register class constraints (#127481)
This fixes a verifier error when folding an immediate materialized into an aligned vgpr class into a copy to an unaligned virtual register.
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2 files changed

+32
-22
lines changed

2 files changed

+32
-22
lines changed

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3473,14 +3473,19 @@ bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
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assert(UseMI.getOperand(1).getReg().isVirtual());
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}
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3476+
MachineFunction *MF = UseMI.getMF();
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const MCInstrDesc &NewMCID = get(NewOpc);
3477-
if (DstReg.isPhysical() &&
3478-
!RI.getRegClass(NewMCID.operands()[0].RegClass)->contains(DstReg))
3478+
const TargetRegisterClass *NewDefRC = getRegClass(NewMCID, 0, &RI, *MF);
3479+
3480+
if (DstReg.isPhysical()) {
3481+
if (!NewDefRC->contains(DstReg))
3482+
return false;
3483+
} else if (!MRI->constrainRegClass(DstReg, NewDefRC))
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return false;
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34813486
UseMI.setDesc(NewMCID);
34823487
UseMI.getOperand(1).ChangeToImmediate(Imm.getSExtValue());
3483-
UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
3488+
UseMI.addImplicitDefUseOperands(*MF);
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return true;
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}
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llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir

Lines changed: 24 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -419,25 +419,30 @@ body: |
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420420
...
421421

422-
# FIXME:
423-
# ---
424-
# name: fold_v_mov_b64_64_to_unaligned
425-
# body: |
426-
# bb.0:
427-
# %0:vreg_64_align2 = V_MOV_B64_e32 1311768467750121200, implicit $exec
428-
# %1:vreg_64 = COPY killed %0
429-
# SI_RETURN_TO_EPILOG implicit %1
430-
# ...
431-
432-
# FIXME:
433-
# ---
434-
# name: fold_v_mov_b64_pseudo_64_to_unaligned
435-
# body: |
436-
# bb.0:
437-
# %0:vreg_64_align2 = V_MOV_B64_PSEUDO 1311768467750121200, implicit $exec
438-
# %1:vreg_64 = COPY killed %0
439-
# SI_RETURN_TO_EPILOG implicit %1
440-
# ...
422+
---
423+
name: fold_v_mov_b64_64_to_unaligned
424+
body: |
425+
bb.0:
426+
; GCN-LABEL: name: fold_v_mov_b64_64_to_unaligned
427+
; GCN: [[V_MOV_B64_e32_:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_e32 1311768467750121200, implicit $exec
428+
; GCN-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 1311768467750121200, implicit $exec
429+
; GCN-NEXT: SI_RETURN_TO_EPILOG implicit [[V_MOV_B]]
430+
%0:vreg_64_align2 = V_MOV_B64_e32 1311768467750121200, implicit $exec
431+
%1:vreg_64 = COPY killed %0
432+
SI_RETURN_TO_EPILOG implicit %1
433+
...
434+
435+
---
436+
name: fold_v_mov_b64_pseudo_64_to_unaligned
437+
body: |
438+
bb.0:
439+
; GCN-LABEL: name: fold_v_mov_b64_pseudo_64_to_unaligned
440+
; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 1311768467750121200, implicit $exec
441+
; GCN-NEXT: SI_RETURN_TO_EPILOG implicit [[V_MOV_B]]
442+
%0:vreg_64_align2 = V_MOV_B64_PSEUDO 1311768467750121200, implicit $exec
443+
%1:vreg_64 = COPY killed %0
444+
SI_RETURN_TO_EPILOG implicit %1
445+
...
441446

442447
---
443448
name: fold_s_brev_b32_simm_virtual_0

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