AMDGPU: Fix foldImmediate breaking register class constraints #127481
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This was referenced Feb 17, 2025
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@llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) ChangesThis fixes a verifier error when folding an immediate materialized Full diff: https://github.com/llvm/llvm-project/pull/127481.diff 2 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 8481c6333f479..0dafa527f722a 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3473,14 +3473,19 @@ bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
assert(UseMI.getOperand(1).getReg().isVirtual());
}
+ MachineFunction *MF = UseMI.getParent()->getParent();
const MCInstrDesc &NewMCID = get(NewOpc);
- if (DstReg.isPhysical() &&
- !RI.getRegClass(NewMCID.operands()[0].RegClass)->contains(DstReg))
+ const TargetRegisterClass *NewDefRC = getRegClass(NewMCID, 0, &RI, *MF);
+
+ if (DstReg.isPhysical()) {
+ if (!NewDefRC->contains(DstReg))
+ return false;
+ } else if (!MRI->constrainRegClass(DstReg, NewDefRC))
return false;
UseMI.setDesc(NewMCID);
UseMI.getOperand(1).ChangeToImmediate(Imm.getSExtValue());
- UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
+ UseMI.addImplicitDefUseOperands(*MF);
return true;
}
diff --git a/llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir b/llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
index cceed6fd008e4..227af34f3fa6f 100644
--- a/llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
+++ b/llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
@@ -419,25 +419,30 @@ body: |
...
-# FIXME:
-# ---
-# name: fold_v_mov_b64_64_to_unaligned
-# body: |
-# bb.0:
-# %0:vreg_64_align2 = V_MOV_B64_e32 1311768467750121200, implicit $exec
-# %1:vreg_64 = COPY killed %0
-# SI_RETURN_TO_EPILOG implicit %1
-# ...
-
-# FIXME:
-# ---
-# name: fold_v_mov_b64_pseudo_64_to_unaligned
-# body: |
-# bb.0:
-# %0:vreg_64_align2 = V_MOV_B64_PSEUDO 1311768467750121200, implicit $exec
-# %1:vreg_64 = COPY killed %0
-# SI_RETURN_TO_EPILOG implicit %1
-# ...
+---
+name: fold_v_mov_b64_64_to_unaligned
+body: |
+ bb.0:
+ ; GCN-LABEL: name: fold_v_mov_b64_64_to_unaligned
+ ; GCN: [[V_MOV_B64_e32_:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_e32 1311768467750121200, implicit $exec
+ ; GCN-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 1311768467750121200, implicit $exec
+ ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit [[V_MOV_B]]
+ %0:vreg_64_align2 = V_MOV_B64_e32 1311768467750121200, implicit $exec
+ %1:vreg_64 = COPY killed %0
+ SI_RETURN_TO_EPILOG implicit %1
+...
+
+---
+name: fold_v_mov_b64_pseudo_64_to_unaligned
+body: |
+ bb.0:
+ ; GCN-LABEL: name: fold_v_mov_b64_pseudo_64_to_unaligned
+ ; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 1311768467750121200, implicit $exec
+ ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit [[V_MOV_B]]
+ %0:vreg_64_align2 = V_MOV_B64_PSEUDO 1311768467750121200, implicit $exec
+ %1:vreg_64 = COPY killed %0
+ SI_RETURN_TO_EPILOG implicit %1
+...
---
name: fold_s_brev_b32_simm_virtual_0
|
cdevadas
reviewed
Feb 17, 2025
| bb.0: | ||
| ; GCN-LABEL: name: fold_v_mov_b64_64_to_unaligned | ||
| ; GCN: [[V_MOV_B64_e32_:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_e32 1311768467750121200, implicit $exec | ||
| ; GCN-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 1311768467750121200, implicit $exec |
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%1 has been forced to *_aling2 after the transformation. I assume it is because the src register in the original copy was of *_aling2.
cdevadas
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Feb 17, 2025
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February 18, 2025 03:31
This fixes a verifier error when folding an immediate materialized into an aligned vgpr class into a copy to an unaligned virtual register.
Co-authored-by: Christudasan Devadasan <[email protected]>
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/73/builds/13184 Here is the relevant piece of the build log for the reference |
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This fixes a verifier error when folding an immediate materialized
into an aligned vgpr class into a copy to an unaligned virtual register.