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Copy file name to clipboardExpand all lines: clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
+18-18Lines changed: 18 additions & 18 deletions
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@@ -260,80 +260,80 @@ svuint64_t xor_u64(svuint64_t a, svuint64_t b) {
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// CHECK-LABEL: @neg_bool(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 16 x i1> [[A:%.*]], shufflevector (<vscale x 16 x i1> insertelement (<vscale x 16 x i1> poison, i1 true, i64 0), <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 16 x i1> [[NEG]]
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// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 16 x i1> [[A:%.*]], splat (i1 true)
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// CHECK-NEXT: ret <vscale x 16 x i1> [[NOT]]
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//
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svbool_tneg_bool(svbool_ta) {
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return ~a;
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}
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// CHECK-LABEL: @neg_i8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -1, i64 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 16 x i8> [[NEG]]
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// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], splat (i8 -1)
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// CHECK-NEXT: ret <vscale x 16 x i8> [[NOT]]
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//
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svint8_tneg_i8(svint8_ta) {
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return ~a;
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}
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// CHECK-LABEL: @neg_i16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -1, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 8 x i16> [[NEG]]
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// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], splat (i16 -1)
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// CHECK-NEXT: ret <vscale x 8 x i16> [[NOT]]
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//
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svint16_tneg_i16(svint16_ta) {
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return ~a;
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}
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// CHECK-LABEL: @neg_i32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 4 x i32> [[NEG]]
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// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], splat (i32 -1)
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// CHECK-NEXT: ret <vscale x 4 x i32> [[NOT]]
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//
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svint32_tneg_i32(svint32_ta) {
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return ~a;
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}
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// CHECK-LABEL: @neg_i64(
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// CHECK-NEXT: entry:
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-
// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 2 x i64> [[NEG]]
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// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], splat (i64 -1)
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// CHECK-NEXT: ret <vscale x 2 x i64> [[NOT]]
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//
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svint64_tneg_i64(svint64_ta) {
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return ~a;
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}
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// CHECK-LABEL: @neg_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -1, i64 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 16 x i8> [[NEG]]
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// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], splat (i8 -1)
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// CHECK-NEXT: ret <vscale x 16 x i8> [[NOT]]
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//
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svuint8_tneg_u8(svuint8_ta) {
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return ~a;
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}
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// CHECK-LABEL: @neg_u16(
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// CHECK-NEXT: entry:
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-
// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -1, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 8 x i16> [[NEG]]
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// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], splat (i16 -1)
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// CHECK-NEXT: ret <vscale x 8 x i16> [[NOT]]
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//
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svuint16_tneg_u16(svuint16_ta) {
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return ~a;
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}
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// CHECK-LABEL: @neg_u32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 4 x i32> [[NEG]]
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// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], splat (i32 -1)
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// CHECK-NEXT: ret <vscale x 4 x i32> [[NOT]]
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//
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svuint32_tneg_u32(svuint32_ta) {
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return ~a;
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}
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// CHECK-LABEL: @neg_u64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 2 x i64> [[NEG]]
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// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], splat (i64 -1)
// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], splat (i32 1)
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> splat (i32 1)
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// CHECK-NEXT: ret <vscale x 4 x i32> [[VECTOR_SELECT]]
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//
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svuint32_tcond_u32_splat(svuint32_t a) {
@@ -188,10 +188,10 @@ svint64_t cond_i64_splat(svint64_t a) {
// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], splat (i64 1)
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> splat (i64 1)
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// CHECK-NEXT: ret <vscale x 2 x i64> [[VECTOR_SELECT]]
Copy file name to clipboardExpand all lines: llvm/test/Assembler/constant-splat.ll
+2-2Lines changed: 2 additions & 2 deletions
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@@ -51,13 +51,13 @@ define <4 x i32> @ret_fixed_lenth_vector_splat_i32() {
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}
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definevoid@add_fixed_lenth_vector_splat_double(<vscale x 2 x double> %a) {
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; CHECK: %add = fadd <vscale x 2 x double> %a, shufflevector (<vscale x 2 x double> insertelement (<vscale x 2 x double> poison, double 5.700000e+00, i64 0), <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer)
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; CHECK: %add = fadd <vscale x 2 x double> %a, splat (double5.700000e+00)
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%add = fadd <vscale x 2 x double> %a, splat (double5.700000e+00)
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retvoid
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}
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define <vscale x 4 x i32> @ret_scalable_vector_splat_i32() {
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; CHECK: ret <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 78, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
Copy file name to clipboardExpand all lines: llvm/test/Bitcode/vscale-shuffle.ll
+2-2Lines changed: 2 additions & 2 deletions
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@@ -2,8 +2,8 @@
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; RUN: verify-uselistorder < %s
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definevoid@f() {
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%l = call <vscale x 16 x i8> @l(<vscale x 16 x i1> shufflevector (<vscale x 16 x i1> insertelement (<vscale x 16 x i1> undef, i1true, i320), <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer))
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%i = add <vscale x 2 x i64> undef, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i641, i320), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer)
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%l = call <vscale x 16 x i8> @l(<vscale x 16 x i1> splat (i1true))
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