[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. #116856

paulwalker-arm · 2024-11-19T18:54:07Z

This brings the printing of scalable vector constant splats inline with their fixed length counterparts.

llvmbot · 2024-11-19T18:54:44Z

@llvm/pr-subscribers-llvm-ir
@llvm/pr-subscribers-llvm-transforms
@llvm/pr-subscribers-mlir-llvm

@llvm/pr-subscribers-clang

Author: Paul Walker (paulwalker-arm)

Changes

This brings the printing of scalable vector constant splats inline with their fixed length counterparts.

Patch is 1.04 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/116856.diff

145 Files Affected:

(modified) clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c (+18-18)
(modified) clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp (+4-4)
(modified) llvm/lib/IR/AsmWriter.cpp (+18)
(modified) llvm/test/Assembler/constant-splat.ll (+2-2)
(modified) llvm/test/Bitcode/vscale-shuffle.ll (+2-2)
(modified) llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll (+35-35)
(modified) llvm/test/CodeGen/AArch64/replace-with-veclib-sleef-scalable.ll (+34-34)
(modified) llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll (+24-24)
(modified) llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll (+2-2)
(modified) llvm/test/Transforms/AggressiveInstCombine/vector-or-load.ll (+1-1)
(modified) llvm/test/Transforms/Attributor/nofpclass.ll (+1-1)
(modified) llvm/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll (+7-13)
(modified) llvm/test/Transforms/ConstraintElimination/geps-ptrvector.ll (+1-1)
(modified) llvm/test/Transforms/CorrelatedValuePropagation/vectors.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-abs-srshl.ll (+13-13)
(modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-fmul-idempotency.ll (+32-21)
(modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-fmul_u-idempotency.ll (+32-21)
(modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-insr.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul-idempotency.ll (+32-21)
(modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul_u-idempotency.ll (+32-21)
(modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sdiv.ll (+3-3)
(modified) llvm/test/Transforms/InstCombine/add.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/div.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/exp2-to-ldexp.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/fdiv.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/fmul.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/fneg.ll (+3-3)
(modified) llvm/test/Transforms/InstCombine/getelementptr.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/icmp-vec.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/known-bits.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/load-store-forward.ll (+10-10)
(modified) llvm/test/Transforms/InstCombine/pow-to-ldexp.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/pr83931.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/scalable-const-fp-splat.ll (+6-3)
(modified) llvm/test/Transforms/InstCombine/scalable-select.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/select-masked_gather.ll (+4-4)
(modified) llvm/test/Transforms/InstCombine/select.ll (+5-5)
(modified) llvm/test/Transforms/InstCombine/shift.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/sub.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/udiv-simplify.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/vec_shuffle.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/vscale_cmp.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll (+2-2)
(modified) llvm/test/Transforms/InstSimplify/ConstProp/extractelement-vscale.ll (+15-9)
(modified) llvm/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll (+6-6)
(modified) llvm/test/Transforms/InstSimplify/ConstProp/vscale-shufflevector-inseltpoison.ll (+11-8)
(modified) llvm/test/Transforms/InstSimplify/ConstProp/vscale-shufflevector.ll (+11-8)
(modified) llvm/test/Transforms/InstSimplify/ConstProp/vscale.ll (+6-6)
(modified) llvm/test/Transforms/InstSimplify/cmp-vec-fast-path.ll (+26-26)
(modified) llvm/test/Transforms/InstSimplify/fp-nan.ll (+10-10)
(modified) llvm/test/Transforms/InstSimplify/gep.ll (+1-1)
(modified) llvm/test/Transforms/InstSimplify/vscale-inseltpoison.ll (+3-3)
(modified) llvm/test/Transforms/InstSimplify/vscale.ll (+3-3)
(modified) llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll (+22-22)
(modified) llvm/test/Transforms/InterleavedAccess/AArch64/sve-deinterleave4.ll (+7-7)
(modified) llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleave4.ll (+5-5)
(modified) llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll (+2-2)
(modified) llvm/test/Transforms/LoopIdiom/RISCV/byte-compare-index.ll (+56-56)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll (+6-6)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll (+3-3)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll (+5-5)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/eliminate-tail-predication.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/gather-do-not-vectorize-addressing.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll (+5-5)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll (+31-31)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll (+19-19)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll (+23-23)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll (+3-3)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll (+47-47)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-basic-vec.ll (+3-3)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll (+9-9)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll (+4-4)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll (+42-42)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll (+16-16)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-large-strides.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll (+16-16)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-optsize.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-overflow-checks.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll (+10-10)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll (+12-12)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll (+4-4)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll (+4-4)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll (+8-8)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-epilogue.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-too-many-deps.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll (+11-11)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-zext-costs.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll (+160-160)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/wider-VF-for-callinst.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/blend-any-of-reduction-cost.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll (+17-17)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll (+9-9)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll (+8-8)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll (+9-9)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll (+8-8)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll (+4-4)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll (+3-3)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll (+3-3)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll (+8-8)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll (+4-4)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll (+4-4)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll (+10-10)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll (+23-23)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll (+10-10)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll (+54-54)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll (+24-24)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll (+33-33)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-intermediate-store.ll (+20-14)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-iv32.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll (+9-9)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-masked-loadstore.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-ordered-reduction.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll (+44-44)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll (+11-11)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-safe-dep-distance.ll (+6-6)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll (+4-4)
(modified) llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll (+7-6)
(modified) llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/scalable-inductions.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/scalable-lifetime.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll (+3-3)
(modified) llvm/test/Transforms/LoopVectorize/scalable-reduction-inloop.ll (+2-2)
(modified) llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll (+1-1)
(modified) llvm/test/Transforms/PreISelIntrinsicLowering/expand-vp-load-store.ll (+2-2)
(modified) llvm/test/Transforms/SCCP/no-fold-fcmp-dynamic-denormal-mode-issue114947.ll (+2-2)
(modified) llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll (+68-68)
(modified) llvm/test/Transforms/VectorCombine/pr88796.ll (+1-1)
(modified) mlir/test/Target/LLVMIR/llvmir.mlir (+1-1)

diff --git a/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c b/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
index 5b97ce44e87365..291d72de42c06f 100644
--- a/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
+++ b/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
@@ -260,8 +260,8 @@ svuint64_t xor_u64(svuint64_t a, svuint64_t b) {
 
 // CHECK-LABEL: @neg_bool(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 16 x i1> [[A:%.*]], shufflevector (<vscale x 16 x i1> insertelement (<vscale x 16 x i1> poison, i1 true, i64 0), <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 16 x i1> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 16 x i1> [[A:%.*]], splat (i1 true)
+// CHECK-NEXT:    ret <vscale x 16 x i1> [[NOT]]
 //
 svbool_t neg_bool(svbool_t a) {
   return ~a;
@@ -269,8 +269,8 @@ svbool_t neg_bool(svbool_t a) {
 
 // CHECK-LABEL: @neg_i8(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -1, i64 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 16 x i8> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], splat (i8 -1)
+// CHECK-NEXT:    ret <vscale x 16 x i8> [[NOT]]
 //
 svint8_t neg_i8(svint8_t a) {
   return ~a;
@@ -278,8 +278,8 @@ svint8_t neg_i8(svint8_t a) {
 
 // CHECK-LABEL: @neg_i16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -1, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 8 x i16> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], splat (i16 -1)
+// CHECK-NEXT:    ret <vscale x 8 x i16> [[NOT]]
 //
 svint16_t neg_i16(svint16_t a) {
   return ~a;
@@ -287,8 +287,8 @@ svint16_t neg_i16(svint16_t a) {
 
 // CHECK-LABEL: @neg_i32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 4 x i32> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], splat (i32 -1)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[NOT]]
 //
 svint32_t neg_i32(svint32_t a) {
   return ~a;
@@ -296,8 +296,8 @@ svint32_t neg_i32(svint32_t a) {
 
 // CHECK-LABEL: @neg_i64(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 2 x i64> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], splat (i64 -1)
+// CHECK-NEXT:    ret <vscale x 2 x i64> [[NOT]]
 //
 svint64_t neg_i64(svint64_t a) {
   return ~a;
@@ -305,8 +305,8 @@ svint64_t neg_i64(svint64_t a) {
 
 // CHECK-LABEL: @neg_u8(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -1, i64 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 16 x i8> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], splat (i8 -1)
+// CHECK-NEXT:    ret <vscale x 16 x i8> [[NOT]]
 //
 svuint8_t neg_u8(svuint8_t a) {
   return ~a;
@@ -314,8 +314,8 @@ svuint8_t neg_u8(svuint8_t a) {
 
 // CHECK-LABEL: @neg_u16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -1, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 8 x i16> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], splat (i16 -1)
+// CHECK-NEXT:    ret <vscale x 8 x i16> [[NOT]]
 //
 svuint16_t neg_u16(svuint16_t a) {
   return ~a;
@@ -323,8 +323,8 @@ svuint16_t neg_u16(svuint16_t a) {
 
 // CHECK-LABEL: @neg_u32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 4 x i32> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], splat (i32 -1)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[NOT]]
 //
 svuint32_t neg_u32(svuint32_t a) {
   return ~a;
@@ -332,8 +332,8 @@ svuint32_t neg_u32(svuint32_t a) {
 
 // CHECK-LABEL: @neg_u64(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 2 x i64> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], splat (i64 -1)
+// CHECK-NEXT:    ret <vscale x 2 x i64> [[NOT]]
 //
 svuint64_t neg_u64(svuint64_t a) {
   return ~a;
diff --git a/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp b/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
index 7e7eff3e02dca5..d6fa26bd340994 100644
--- a/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
+++ b/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
@@ -164,10 +164,10 @@ svint32_t cond_i32_splat(svint32_t a) {
 
 // CHECK-LABEL: @_Z14cond_u32_splatu12__SVUint32_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+// CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], splat (i32 1)
 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 // CHECK-NEXT:    [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
-// CHECK-NEXT:    [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+// CHECK-NEXT:    [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> splat (i32 1)
 // CHECK-NEXT:    ret <vscale x 4 x i32> [[VECTOR_SELECT]]
 //
 svuint32_t cond_u32_splat(svuint32_t a) {
@@ -188,10 +188,10 @@ svint64_t cond_i64_splat(svint64_t a) {
 
 // CHECK-LABEL: @_Z14cond_u64_splatu12__SVUint64_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
+// CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], splat (i64 1)
 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 // CHECK-NEXT:    [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
-// CHECK-NEXT:    [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
+// CHECK-NEXT:    [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> splat (i64 1)
 // CHECK-NEXT:    ret <vscale x 2 x i64> [[VECTOR_SELECT]]
 //
 svuint64_t cond_u64_splat(svuint64_t a) {
diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp
index f6a5bc10ff3b23..f8183774f4056d 100644
--- a/llvm/lib/IR/AsmWriter.cpp
+++ b/llvm/lib/IR/AsmWriter.cpp
@@ -1741,6 +1741,24 @@ static void WriteConstantInternal(raw_ostream &Out, const Constant *CV,
   }
 
   if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV)) {
+    // Use the same shorthand for splat vector (i.e. "splat(Ty val)") as is
+    // permitted on IR input to reduce the output changes when enabling
+    // UseConstant{Int,FP}ForScalableSplat.
+    // TODO: Remove this block when the UseConstant{Int,FP}ForScalableSplat
+    // options are removed.
+    if (CE->getOpcode() == Instruction::ShuffleVector) {
+      if (auto *SplatVal = CE->getSplatValue()) {
+        if (isa<ConstantInt>(SplatVal) || isa<ConstantFP>(SplatVal)) {
+          Out << "splat (";
+          WriterCtx.TypePrinter->print(SplatVal->getType(), Out);
+          Out << ' ';
+          WriteAsOperandInternal(Out, SplatVal, WriterCtx);
+          Out << ')';
+          return;
+        }
+      }
+    }
+
     Out << CE->getOpcodeName();
     WriteOptimizationInfo(Out, CE);
     Out << " (";
diff --git a/llvm/test/Assembler/constant-splat.ll b/llvm/test/Assembler/constant-splat.ll
index 1c2831058b8870..82e25adda0e108 100644
--- a/llvm/test/Assembler/constant-splat.ll
+++ b/llvm/test/Assembler/constant-splat.ll
@@ -51,13 +51,13 @@ define <4 x i32> @ret_fixed_lenth_vector_splat_i32() {
 }
 
 define void @add_fixed_lenth_vector_splat_double(<vscale x 2 x double> %a) {
-; CHECK: %add = fadd <vscale x 2 x double> %a, shufflevector (<vscale x 2 x double> insertelement (<vscale x 2 x double> poison, double 5.700000e+00, i64 0), <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer)
+; CHECK: %add = fadd <vscale x 2 x double> %a, splat (double 5.700000e+00)
   %add = fadd <vscale x 2 x double> %a, splat (double 5.700000e+00)
   ret void
 }
 
 define <vscale x 4 x i32> @ret_scalable_vector_splat_i32() {
-; CHECK: ret <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 78, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+; CHECK: ret <vscale x 4 x i32> splat (i32 78)
   ret <vscale x 4 x i32> splat (i32 78)
 }
 
diff --git a/llvm/test/Bitcode/vscale-shuffle.ll b/llvm/test/Bitcode/vscale-shuffle.ll
index 3f36209c7aaf50..f92794961b61e0 100644
--- a/llvm/test/Bitcode/vscale-shuffle.ll
+++ b/llvm/test/Bitcode/vscale-shuffle.ll
@@ -2,8 +2,8 @@
 ; RUN: verify-uselistorder < %s
 
 define void @f() {
-  %l = call <vscale x 16 x i8> @l(<vscale x 16 x i1> shufflevector (<vscale x 16 x i1> insertelement (<vscale x 16 x i1> undef, i1 true, i32 0), <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer))
-  %i = add <vscale x 2 x i64> undef, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 1, i32 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer)
+  %l = call <vscale x 16 x i8> @l(<vscale x 16 x i1> splat (i1 true))
+  %i = add <vscale x 2 x i64> undef, splat (i64 1)
   unreachable
 }
 
diff --git a/llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll b/llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll
index 26fb4ca602da17..71c6380177b3a4 100644
--- a/llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll
+++ b/llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll
@@ -14,9 +14,9 @@ declare <4 x float> @llvm.cos.v4f32(<4 x float>)
 declare <vscale x 2 x double> @llvm.cos.nxv2f64(<vscale x 2 x double>)
 declare <vscale x 4 x float> @llvm.cos.nxv4f32(<vscale x 4 x float>)
 
+
 ;.
 ; CHECK: @llvm.compiler.used = appending global [68 x ptr] [ptr @armpl_vcosq_f64, ptr @armpl_vcosq_f32, ptr @armpl_svcos_f64_x, ptr @armpl_svcos_f32_x, ptr @armpl_vexpq_f64, ptr @armpl_vexpq_f32, ptr @armpl_svexp_f64_x, ptr @armpl_svexp_f32_x, ptr @armpl_vexp10q_f64, ptr @armpl_vexp10q_f32, ptr @armpl_svexp10_f64_x, ptr @armpl_svexp10_f32_x, ptr @armpl_vexp2q_f64, ptr @armpl_vexp2q_f32, ptr @armpl_svexp2_f64_x, ptr @armpl_svexp2_f32_x, ptr @armpl_vlogq_f64, ptr @armpl_vlogq_f32, ptr @armpl_svlog_f64_x, ptr @armpl_svlog_f32_x, ptr @armpl_vlog10q_f64, ptr @armpl_vlog10q_f32, ptr @armpl_svlog10_f64_x, ptr @armpl_svlog10_f32_x, ptr @armpl_vlog2q_f64, ptr @armpl_vlog2q_f32, ptr @armpl_svlog2_f64_x, ptr @armpl_svlog2_f32_x, ptr @armpl_vpowq_f64, ptr @armpl_vpowq_f32, ptr @armpl_svpow_f64_x, ptr @armpl_svpow_f32_x, ptr @armpl_vsinq_f64, ptr @armpl_vsinq_f32, ptr @armpl_svsin_f64_x, ptr @armpl_svsin_f32_x, ptr @armpl_vtanq_f64, ptr @armpl_vtanq_f32, ptr @armpl_svtan_f64_x, ptr @armpl_svtan_f32_x, ptr @armpl_vacosq_f64, ptr @armpl_vacosq_f32, ptr @armpl_svacos_f64_x, ptr @armpl_svacos_f32_x, ptr @armpl_vasinq_f64, ptr @armpl_vasinq_f32, ptr @armpl_svasin_f64_x, ptr @armpl_svasin_f32_x, ptr @armpl_vatanq_f64, ptr @armpl_vatanq_f32, ptr @armpl_svatan_f64_x, ptr @armpl_svatan_f32_x, ptr @armpl_vatan2q_f64, ptr @armpl_vatan2q_f32, ptr @armpl_svatan2_f64_x, ptr @armpl_svatan2_f32_x, ptr @armpl_vcoshq_f64, ptr @armpl_vcoshq_f32, ptr @armpl_svcosh_f64_x, ptr @armpl_svcosh_f32_x, ptr @armpl_vsinhq_f64, ptr @armpl_vsinhq_f32, ptr @armpl_svsinh_f64_x, ptr @armpl_svsinh_f32_x, ptr @armpl_vtanhq_f64, ptr @armpl_vtanhq_f32, ptr @armpl_svtanh_f64_x, ptr @armpl_svtanh_f32_x], section "llvm.metadata"
-
 ;.
 define <2 x double> @llvm_cos_f64(<2 x double> %in) {
 ; CHECK-LABEL: define <2 x double> @llvm_cos_f64
@@ -41,7 +41,7 @@ define <4 x float> @llvm_cos_f32(<4 x float> %in) {
 define <vscale x 2 x double> @llvm_cos_vscale_f64(<vscale x 2 x double> %in) #0 {
 ; CHECK-LABEL: define <vscale x 2 x double> @llvm_cos_vscale_f64
 ; CHECK-SAME: (<vscale x 2 x double> [[IN:%.*]]) #[[ATTR1:[0-9]+]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svcos_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svcos_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 ;
   %1 = call fast <vscale x 2 x double> @llvm.cos.nxv2f64(<vscale x 2 x double> %in)
@@ -51,7 +51,7 @@ define <vscale x 2 x double> @llvm_cos_vscale_f64(<vscale x 2 x double> %in) #0
 define <vscale x 4 x float> @llvm_cos_vscale_f32(<vscale x 4 x float> %in) #0 {
 ; CHECK-LABEL: define <vscale x 4 x float> @llvm_cos_vscale_f32
 ; CHECK-SAME: (<vscale x 4 x float> [[IN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svcos_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i64 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svcos_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 ;
   %1 = call fast <vscale x 4 x float> @llvm.cos.nxv4f32(<vscale x 4 x float> %in)
@@ -86,7 +86,7 @@ define <4 x float> @llvm_exp_f32(<4 x float> %in) {
 define <vscale x 2 x double> @llvm_exp_vscale_f64(<vscale x 2 x double> %in) #0 {
 ; CHECK-LABEL: define <vscale x 2 x double> @llvm_exp_vscale_f64
 ; CHECK-SAME: (<vscale x 2 x double> [[IN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svexp_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svexp_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 ;
   %1 = call fast <vscale x 2 x double> @llvm.exp.nxv2f64(<vscale x 2 x double> %in)
@@ -96,7 +96,7 @@ define <vscale x 2 x double> @llvm_exp_vscale_f64(<vscale x 2 x double> %in) #0
 define <vscale x 4 x float> @llvm_exp_vscale_f32(<vscale x 4 x float> %in) #0 {
 ; CHECK-LABEL: define <vscale x 4 x float> @llvm_exp_vscale_f32
 ; CHECK-SAME: (<vscale x 4 x float> [[IN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svexp_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i64 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svexp_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 ;
   %1 = call fast <vscale x 4 x float> @llvm.exp.nxv4f32(<vscale x 4 x float> %in)
@@ -131,7 +131,7 @@ define <4 x float> @llvm_exp10_f32(<4 x float> %in) {
 define <vscale x 2 x double> @llvm_exp10_vscale_f64(<vscale x 2 x double> %in) #0 {
 ; CHECK-LABEL: define <vscale x 2 x double> @llvm_exp10_vscale_f64
 ; CHECK-SAME: (<vscale x 2 x double> [[IN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svexp10_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svexp10_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 ;
   %1 = call fast <vscale x 2 x double> @llvm.exp10.nxv2f64(<vscale x 2 x double> %in)
@@ -141,7 +141,7 @@ define <vscale x 2 x double> @llvm_exp10_vscale_f64(<vscale x 2 x double> %in) #
 define <vscale x 4 x float> @llvm_exp10_vscale_f32(<vscale x 4 x float> %in) #0 {
 ; CHECK-LABEL: define <vscale x 4 x float> @llvm_exp10_vscale_f32
 ; CHECK-SAME: (<vscale x 4 x float> [[IN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svexp10_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i64 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svexp10_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 ;
   %1 = call fast <vscale x 4 x float> @llvm.exp10.nxv4f32(<vscale x 4 x float> %in)
@@ -176,7 +176,7 @@ define <4 x float> @llvm_exp2_f32(<4 x float> %in) {
 define <vscale x 2 x double> @llvm_exp2_vscale_f64(<vscale x 2 x double> %in) #0 {
 ; CHECK-LABEL: define <vscale x 2 x double> @llvm_exp2_vscale_f64
 ; CHECK-SAME: (<vscale x 2 x double> [[IN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svexp2_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svexp2_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 ;
   %1 = call fast <vscale x 2 x double> @llvm.exp2.nxv2f64(<vscale x 2 x double> %in)
@@ -186,7 +186,7 @@ define <vscale x 2 x double> @llvm_exp2_vscale_f64(<vscale x 2 x double> %in) #0
 define <vscale x 4 x float> @llvm_exp2_vscale_f32(<vscale x 4 x float> %in) #0 {
 ; CHECK-LABEL: define <vscale x 4 x float> @llvm_exp2_vscale_f32
 ; CHECK-SAME: (<vscale x 4 x float> [[IN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svexp2_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i64 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svexp2_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 ;
   %1 = call fast <vscale x 4 x float> @llvm.exp2.nxv4f32(<vscale x 4 x float> %in)
@@ -221,7 +221,7 @@ define <4 x float> @llvm_log_f32(<4 x float> %in) ...
[truncated]

llvmbot · 2024-11-19T18:54:45Z

@llvm/pr-subscribers-backend-aarch64

Author: Paul Walker (paulwalker-arm)

Changes

This brings the printing of scalable vector constant splats inline with their fixed length counterparts.

Patch is 1.04 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/116856.diff

145 Files Affected:

(modified) clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c (+18-18)
(modified) clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp (+4-4)
(modified) llvm/lib/IR/AsmWriter.cpp (+18)
(modified) llvm/test/Assembler/constant-splat.ll (+2-2)
(modified) llvm/test/Bitcode/vscale-shuffle.ll (+2-2)
(modified) llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll (+35-35)
(modified) llvm/test/CodeGen/AArch64/replace-with-veclib-sleef-scalable.ll (+34-34)
(modified) llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll (+24-24)
(modified) llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll (+2-2)
(modified) llvm/test/Transforms/AggressiveInstCombine/vector-or-load.ll (+1-1)
(modified) llvm/test/Transforms/Attributor/nofpclass.ll (+1-1)
(modified) llvm/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll (+7-13)
(modified) llvm/test/Transforms/ConstraintElimination/geps-ptrvector.ll (+1-1)
(modified) llvm/test/Transforms/CorrelatedValuePropagation/vectors.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-abs-srshl.ll (+13-13)
(modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-fmul-idempotency.ll (+32-21)
(modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-fmul_u-idempotency.ll (+32-21)
(modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-insr.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul-idempotency.ll (+32-21)
(modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-mul_u-idempotency.ll (+32-21)
(modified) llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sdiv.ll (+3-3)
(modified) llvm/test/Transforms/InstCombine/add.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/div.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/exp2-to-ldexp.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/fdiv.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/fmul.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/fneg.ll (+3-3)
(modified) llvm/test/Transforms/InstCombine/getelementptr.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/icmp-vec.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/known-bits.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/load-store-forward.ll (+10-10)
(modified) llvm/test/Transforms/InstCombine/pow-to-ldexp.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/pr83931.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/scalable-const-fp-splat.ll (+6-3)
(modified) llvm/test/Transforms/InstCombine/scalable-select.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/select-masked_gather.ll (+4-4)
(modified) llvm/test/Transforms/InstCombine/select.ll (+5-5)
(modified) llvm/test/Transforms/InstCombine/shift.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/sub.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/udiv-simplify.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/vec_shuffle.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/vscale_cmp.ll (+1-1)
(modified) llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll (+2-2)
(modified) llvm/test/Transforms/InstSimplify/ConstProp/extractelement-vscale.ll (+15-9)
(modified) llvm/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll (+6-6)
(modified) llvm/test/Transforms/InstSimplify/ConstProp/vscale-shufflevector-inseltpoison.ll (+11-8)
(modified) llvm/test/Transforms/InstSimplify/ConstProp/vscale-shufflevector.ll (+11-8)
(modified) llvm/test/Transforms/InstSimplify/ConstProp/vscale.ll (+6-6)
(modified) llvm/test/Transforms/InstSimplify/cmp-vec-fast-path.ll (+26-26)
(modified) llvm/test/Transforms/InstSimplify/fp-nan.ll (+10-10)
(modified) llvm/test/Transforms/InstSimplify/gep.ll (+1-1)
(modified) llvm/test/Transforms/InstSimplify/vscale-inseltpoison.ll (+3-3)
(modified) llvm/test/Transforms/InstSimplify/vscale.ll (+3-3)
(modified) llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll (+22-22)
(modified) llvm/test/Transforms/InterleavedAccess/AArch64/sve-deinterleave4.ll (+7-7)
(modified) llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleave4.ll (+5-5)
(modified) llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll (+2-2)
(modified) llvm/test/Transforms/LoopIdiom/RISCV/byte-compare-index.ll (+56-56)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll (+6-6)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll (+3-3)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll (+5-5)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/eliminate-tail-predication.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/gather-do-not-vectorize-addressing.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll (+5-5)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll (+31-31)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll (+19-19)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll (+23-23)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/scalable-reduction-inloop-cond.ll (+3-3)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll (+47-47)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-basic-vec.ll (+3-3)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll (+9-9)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll (+4-4)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll (+42-42)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll (+16-16)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-large-strides.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll (+16-16)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-optsize.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-overflow-checks.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll (+10-10)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll (+12-12)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll (+4-4)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll (+4-4)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll (+8-8)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-epilogue.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-too-many-deps.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll (+11-11)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/tail-folding-styles.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-zext-costs.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll (+160-160)
(modified) llvm/test/Transforms/LoopVectorize/AArch64/wider-VF-for-callinst.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/blend-any-of-reduction-cost.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll (+17-17)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll (+9-9)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll (+8-8)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll (+9-9)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll (+8-8)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll (+4-4)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll (+3-3)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll (+3-3)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll (+8-8)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll (+4-4)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll (+4-4)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll (+10-10)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll (+23-23)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll (+10-10)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll (+54-54)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll (+24-24)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-inloop-reduction.ll (+33-33)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-intermediate-store.ll (+20-14)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-iv32.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-known-no-overflow.ll (+9-9)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-masked-loadstore.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-ordered-reduction.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll (+44-44)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll (+11-11)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-safe-dep-distance.ll (+6-6)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll (+4-4)
(modified) llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll (+7-6)
(modified) llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll (+1-1)
(modified) llvm/test/Transforms/LoopVectorize/scalable-inductions.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/scalable-lifetime.ll (+2-2)
(modified) llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll (+3-3)
(modified) llvm/test/Transforms/LoopVectorize/scalable-reduction-inloop.ll (+2-2)
(modified) llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll (+1-1)
(modified) llvm/test/Transforms/PreISelIntrinsicLowering/expand-vp-load-store.ll (+2-2)
(modified) llvm/test/Transforms/SCCP/no-fold-fcmp-dynamic-denormal-mode-issue114947.ll (+2-2)
(modified) llvm/test/Transforms/VectorCombine/RISCV/vpintrin-scalarization.ll (+68-68)
(modified) llvm/test/Transforms/VectorCombine/pr88796.ll (+1-1)
(modified) mlir/test/Target/LLVMIR/llvmir.mlir (+1-1)

diff --git a/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c b/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
index 5b97ce44e87365..291d72de42c06f 100644
--- a/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
+++ b/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
@@ -260,8 +260,8 @@ svuint64_t xor_u64(svuint64_t a, svuint64_t b) {
 
 // CHECK-LABEL: @neg_bool(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 16 x i1> [[A:%.*]], shufflevector (<vscale x 16 x i1> insertelement (<vscale x 16 x i1> poison, i1 true, i64 0), <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 16 x i1> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 16 x i1> [[A:%.*]], splat (i1 true)
+// CHECK-NEXT:    ret <vscale x 16 x i1> [[NOT]]
 //
 svbool_t neg_bool(svbool_t a) {
   return ~a;
@@ -269,8 +269,8 @@ svbool_t neg_bool(svbool_t a) {
 
 // CHECK-LABEL: @neg_i8(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -1, i64 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 16 x i8> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], splat (i8 -1)
+// CHECK-NEXT:    ret <vscale x 16 x i8> [[NOT]]
 //
 svint8_t neg_i8(svint8_t a) {
   return ~a;
@@ -278,8 +278,8 @@ svint8_t neg_i8(svint8_t a) {
 
 // CHECK-LABEL: @neg_i16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -1, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 8 x i16> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], splat (i16 -1)
+// CHECK-NEXT:    ret <vscale x 8 x i16> [[NOT]]
 //
 svint16_t neg_i16(svint16_t a) {
   return ~a;
@@ -287,8 +287,8 @@ svint16_t neg_i16(svint16_t a) {
 
 // CHECK-LABEL: @neg_i32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 4 x i32> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], splat (i32 -1)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[NOT]]
 //
 svint32_t neg_i32(svint32_t a) {
   return ~a;
@@ -296,8 +296,8 @@ svint32_t neg_i32(svint32_t a) {
 
 // CHECK-LABEL: @neg_i64(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 2 x i64> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], splat (i64 -1)
+// CHECK-NEXT:    ret <vscale x 2 x i64> [[NOT]]
 //
 svint64_t neg_i64(svint64_t a) {
   return ~a;
@@ -305,8 +305,8 @@ svint64_t neg_i64(svint64_t a) {
 
 // CHECK-LABEL: @neg_u8(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -1, i64 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 16 x i8> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], splat (i8 -1)
+// CHECK-NEXT:    ret <vscale x 16 x i8> [[NOT]]
 //
 svuint8_t neg_u8(svuint8_t a) {
   return ~a;
@@ -314,8 +314,8 @@ svuint8_t neg_u8(svuint8_t a) {
 
 // CHECK-LABEL: @neg_u16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -1, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 8 x i16> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], splat (i16 -1)
+// CHECK-NEXT:    ret <vscale x 8 x i16> [[NOT]]
 //
 svuint16_t neg_u16(svuint16_t a) {
   return ~a;
@@ -323,8 +323,8 @@ svuint16_t neg_u16(svuint16_t a) {
 
 // CHECK-LABEL: @neg_u32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 4 x i32> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], splat (i32 -1)
+// CHECK-NEXT:    ret <vscale x 4 x i32> [[NOT]]
 //
 svuint32_t neg_u32(svuint32_t a) {
   return ~a;
@@ -332,8 +332,8 @@ svuint32_t neg_u32(svuint32_t a) {
 
 // CHECK-LABEL: @neg_u64(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[NEG:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
-// CHECK-NEXT:    ret <vscale x 2 x i64> [[NEG]]
+// CHECK-NEXT:    [[NOT:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], splat (i64 -1)
+// CHECK-NEXT:    ret <vscale x 2 x i64> [[NOT]]
 //
 svuint64_t neg_u64(svuint64_t a) {
   return ~a;
diff --git a/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp b/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
index 7e7eff3e02dca5..d6fa26bd340994 100644
--- a/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
+++ b/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
@@ -164,10 +164,10 @@ svint32_t cond_i32_splat(svint32_t a) {
 
 // CHECK-LABEL: @_Z14cond_u32_splatu12__SVUint32_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+// CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], splat (i32 1)
 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 // CHECK-NEXT:    [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
-// CHECK-NEXT:    [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+// CHECK-NEXT:    [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> splat (i32 1)
 // CHECK-NEXT:    ret <vscale x 4 x i32> [[VECTOR_SELECT]]
 //
 svuint32_t cond_u32_splat(svuint32_t a) {
@@ -188,10 +188,10 @@ svint64_t cond_i64_splat(svint64_t a) {
 
 // CHECK-LABEL: @_Z14cond_u64_splatu12__SVUint64_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
+// CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], splat (i64 1)
 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 // CHECK-NEXT:    [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
-// CHECK-NEXT:    [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
+// CHECK-NEXT:    [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> splat (i64 1)
 // CHECK-NEXT:    ret <vscale x 2 x i64> [[VECTOR_SELECT]]
 //
 svuint64_t cond_u64_splat(svuint64_t a) {
diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp
index f6a5bc10ff3b23..f8183774f4056d 100644
--- a/llvm/lib/IR/AsmWriter.cpp
+++ b/llvm/lib/IR/AsmWriter.cpp
@@ -1741,6 +1741,24 @@ static void WriteConstantInternal(raw_ostream &Out, const Constant *CV,
   }
 
   if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV)) {
+    // Use the same shorthand for splat vector (i.e. "splat(Ty val)") as is
+    // permitted on IR input to reduce the output changes when enabling
+    // UseConstant{Int,FP}ForScalableSplat.
+    // TODO: Remove this block when the UseConstant{Int,FP}ForScalableSplat
+    // options are removed.
+    if (CE->getOpcode() == Instruction::ShuffleVector) {
+      if (auto *SplatVal = CE->getSplatValue()) {
+        if (isa<ConstantInt>(SplatVal) || isa<ConstantFP>(SplatVal)) {
+          Out << "splat (";
+          WriterCtx.TypePrinter->print(SplatVal->getType(), Out);
+          Out << ' ';
+          WriteAsOperandInternal(Out, SplatVal, WriterCtx);
+          Out << ')';
+          return;
+        }
+      }
+    }
+
     Out << CE->getOpcodeName();
     WriteOptimizationInfo(Out, CE);
     Out << " (";
diff --git a/llvm/test/Assembler/constant-splat.ll b/llvm/test/Assembler/constant-splat.ll
index 1c2831058b8870..82e25adda0e108 100644
--- a/llvm/test/Assembler/constant-splat.ll
+++ b/llvm/test/Assembler/constant-splat.ll
@@ -51,13 +51,13 @@ define <4 x i32> @ret_fixed_lenth_vector_splat_i32() {
 }
 
 define void @add_fixed_lenth_vector_splat_double(<vscale x 2 x double> %a) {
-; CHECK: %add = fadd <vscale x 2 x double> %a, shufflevector (<vscale x 2 x double> insertelement (<vscale x 2 x double> poison, double 5.700000e+00, i64 0), <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer)
+; CHECK: %add = fadd <vscale x 2 x double> %a, splat (double 5.700000e+00)
   %add = fadd <vscale x 2 x double> %a, splat (double 5.700000e+00)
   ret void
 }
 
 define <vscale x 4 x i32> @ret_scalable_vector_splat_i32() {
-; CHECK: ret <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 78, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+; CHECK: ret <vscale x 4 x i32> splat (i32 78)
   ret <vscale x 4 x i32> splat (i32 78)
 }
 
diff --git a/llvm/test/Bitcode/vscale-shuffle.ll b/llvm/test/Bitcode/vscale-shuffle.ll
index 3f36209c7aaf50..f92794961b61e0 100644
--- a/llvm/test/Bitcode/vscale-shuffle.ll
+++ b/llvm/test/Bitcode/vscale-shuffle.ll
@@ -2,8 +2,8 @@
 ; RUN: verify-uselistorder < %s
 
 define void @f() {
-  %l = call <vscale x 16 x i8> @l(<vscale x 16 x i1> shufflevector (<vscale x 16 x i1> insertelement (<vscale x 16 x i1> undef, i1 true, i32 0), <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer))
-  %i = add <vscale x 2 x i64> undef, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 1, i32 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer)
+  %l = call <vscale x 16 x i8> @l(<vscale x 16 x i1> splat (i1 true))
+  %i = add <vscale x 2 x i64> undef, splat (i64 1)
   unreachable
 }
 
diff --git a/llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll b/llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll
index 26fb4ca602da17..71c6380177b3a4 100644
--- a/llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll
+++ b/llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll
@@ -14,9 +14,9 @@ declare <4 x float> @llvm.cos.v4f32(<4 x float>)
 declare <vscale x 2 x double> @llvm.cos.nxv2f64(<vscale x 2 x double>)
 declare <vscale x 4 x float> @llvm.cos.nxv4f32(<vscale x 4 x float>)
 
+
 ;.
 ; CHECK: @llvm.compiler.used = appending global [68 x ptr] [ptr @armpl_vcosq_f64, ptr @armpl_vcosq_f32, ptr @armpl_svcos_f64_x, ptr @armpl_svcos_f32_x, ptr @armpl_vexpq_f64, ptr @armpl_vexpq_f32, ptr @armpl_svexp_f64_x, ptr @armpl_svexp_f32_x, ptr @armpl_vexp10q_f64, ptr @armpl_vexp10q_f32, ptr @armpl_svexp10_f64_x, ptr @armpl_svexp10_f32_x, ptr @armpl_vexp2q_f64, ptr @armpl_vexp2q_f32, ptr @armpl_svexp2_f64_x, ptr @armpl_svexp2_f32_x, ptr @armpl_vlogq_f64, ptr @armpl_vlogq_f32, ptr @armpl_svlog_f64_x, ptr @armpl_svlog_f32_x, ptr @armpl_vlog10q_f64, ptr @armpl_vlog10q_f32, ptr @armpl_svlog10_f64_x, ptr @armpl_svlog10_f32_x, ptr @armpl_vlog2q_f64, ptr @armpl_vlog2q_f32, ptr @armpl_svlog2_f64_x, ptr @armpl_svlog2_f32_x, ptr @armpl_vpowq_f64, ptr @armpl_vpowq_f32, ptr @armpl_svpow_f64_x, ptr @armpl_svpow_f32_x, ptr @armpl_vsinq_f64, ptr @armpl_vsinq_f32, ptr @armpl_svsin_f64_x, ptr @armpl_svsin_f32_x, ptr @armpl_vtanq_f64, ptr @armpl_vtanq_f32, ptr @armpl_svtan_f64_x, ptr @armpl_svtan_f32_x, ptr @armpl_vacosq_f64, ptr @armpl_vacosq_f32, ptr @armpl_svacos_f64_x, ptr @armpl_svacos_f32_x, ptr @armpl_vasinq_f64, ptr @armpl_vasinq_f32, ptr @armpl_svasin_f64_x, ptr @armpl_svasin_f32_x, ptr @armpl_vatanq_f64, ptr @armpl_vatanq_f32, ptr @armpl_svatan_f64_x, ptr @armpl_svatan_f32_x, ptr @armpl_vatan2q_f64, ptr @armpl_vatan2q_f32, ptr @armpl_svatan2_f64_x, ptr @armpl_svatan2_f32_x, ptr @armpl_vcoshq_f64, ptr @armpl_vcoshq_f32, ptr @armpl_svcosh_f64_x, ptr @armpl_svcosh_f32_x, ptr @armpl_vsinhq_f64, ptr @armpl_vsinhq_f32, ptr @armpl_svsinh_f64_x, ptr @armpl_svsinh_f32_x, ptr @armpl_vtanhq_f64, ptr @armpl_vtanhq_f32, ptr @armpl_svtanh_f64_x, ptr @armpl_svtanh_f32_x], section "llvm.metadata"
-
 ;.
 define <2 x double> @llvm_cos_f64(<2 x double> %in) {
 ; CHECK-LABEL: define <2 x double> @llvm_cos_f64
@@ -41,7 +41,7 @@ define <4 x float> @llvm_cos_f32(<4 x float> %in) {
 define <vscale x 2 x double> @llvm_cos_vscale_f64(<vscale x 2 x double> %in) #0 {
 ; CHECK-LABEL: define <vscale x 2 x double> @llvm_cos_vscale_f64
 ; CHECK-SAME: (<vscale x 2 x double> [[IN:%.*]]) #[[ATTR1:[0-9]+]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svcos_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svcos_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 ;
   %1 = call fast <vscale x 2 x double> @llvm.cos.nxv2f64(<vscale x 2 x double> %in)
@@ -51,7 +51,7 @@ define <vscale x 2 x double> @llvm_cos_vscale_f64(<vscale x 2 x double> %in) #0
 define <vscale x 4 x float> @llvm_cos_vscale_f32(<vscale x 4 x float> %in) #0 {
 ; CHECK-LABEL: define <vscale x 4 x float> @llvm_cos_vscale_f32
 ; CHECK-SAME: (<vscale x 4 x float> [[IN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svcos_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i64 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svcos_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 ;
   %1 = call fast <vscale x 4 x float> @llvm.cos.nxv4f32(<vscale x 4 x float> %in)
@@ -86,7 +86,7 @@ define <4 x float> @llvm_exp_f32(<4 x float> %in) {
 define <vscale x 2 x double> @llvm_exp_vscale_f64(<vscale x 2 x double> %in) #0 {
 ; CHECK-LABEL: define <vscale x 2 x double> @llvm_exp_vscale_f64
 ; CHECK-SAME: (<vscale x 2 x double> [[IN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svexp_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svexp_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 ;
   %1 = call fast <vscale x 2 x double> @llvm.exp.nxv2f64(<vscale x 2 x double> %in)
@@ -96,7 +96,7 @@ define <vscale x 2 x double> @llvm_exp_vscale_f64(<vscale x 2 x double> %in) #0
 define <vscale x 4 x float> @llvm_exp_vscale_f32(<vscale x 4 x float> %in) #0 {
 ; CHECK-LABEL: define <vscale x 4 x float> @llvm_exp_vscale_f32
 ; CHECK-SAME: (<vscale x 4 x float> [[IN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svexp_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i64 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svexp_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 ;
   %1 = call fast <vscale x 4 x float> @llvm.exp.nxv4f32(<vscale x 4 x float> %in)
@@ -131,7 +131,7 @@ define <4 x float> @llvm_exp10_f32(<4 x float> %in) {
 define <vscale x 2 x double> @llvm_exp10_vscale_f64(<vscale x 2 x double> %in) #0 {
 ; CHECK-LABEL: define <vscale x 2 x double> @llvm_exp10_vscale_f64
 ; CHECK-SAME: (<vscale x 2 x double> [[IN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svexp10_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svexp10_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 ;
   %1 = call fast <vscale x 2 x double> @llvm.exp10.nxv2f64(<vscale x 2 x double> %in)
@@ -141,7 +141,7 @@ define <vscale x 2 x double> @llvm_exp10_vscale_f64(<vscale x 2 x double> %in) #
 define <vscale x 4 x float> @llvm_exp10_vscale_f32(<vscale x 4 x float> %in) #0 {
 ; CHECK-LABEL: define <vscale x 4 x float> @llvm_exp10_vscale_f32
 ; CHECK-SAME: (<vscale x 4 x float> [[IN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svexp10_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i64 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svexp10_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 ;
   %1 = call fast <vscale x 4 x float> @llvm.exp10.nxv4f32(<vscale x 4 x float> %in)
@@ -176,7 +176,7 @@ define <4 x float> @llvm_exp2_f32(<4 x float> %in) {
 define <vscale x 2 x double> @llvm_exp2_vscale_f64(<vscale x 2 x double> %in) #0 {
 ; CHECK-LABEL: define <vscale x 2 x double> @llvm_exp2_vscale_f64
 ; CHECK-SAME: (<vscale x 2 x double> [[IN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svexp2_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 2 x double> @armpl_svexp2_f64_x(<vscale x 2 x double> [[IN]], <vscale x 2 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 ;
   %1 = call fast <vscale x 2 x double> @llvm.exp2.nxv2f64(<vscale x 2 x double> %in)
@@ -186,7 +186,7 @@ define <vscale x 2 x double> @llvm_exp2_vscale_f64(<vscale x 2 x double> %in) #0
 define <vscale x 4 x float> @llvm_exp2_vscale_f32(<vscale x 4 x float> %in) #0 {
 ; CHECK-LABEL: define <vscale x 4 x float> @llvm_exp2_vscale_f32
 ; CHECK-SAME: (<vscale x 4 x float> [[IN:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svexp2_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i64 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer))
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <vscale x 4 x float> @armpl_svexp2_f32_x(<vscale x 4 x float> [[IN]], <vscale x 4 x i1> splat (i1 true))
 ; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 ;
   %1 = call fast <vscale x 4 x float> @llvm.exp2.nxv4f32(<vscale x 4 x float> %in)
@@ -221,7 +221,7 @@ define <4 x float> @llvm_log_f32(<4 x float> %in) ...
[truncated]

nikic

LGTM

llvmbot added clang Clang issues not falling into any other category backend:AArch64 mlir:llvm mlir llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:ir llvm:transforms labels Nov 19, 2024

paulwalker-arm added 2 commits November 20, 2024 12:51

[LLVM][IR] Use splat syntax when printing ConstantExpr based splats.

554e49b

Regenerate CHECK lines.

519968e

paulwalker-arm force-pushed the vector-constants-ir-printing branch from a8f41e4 to 519968e Compare November 20, 2024 13:04

paulwalker-arm requested review from arsenm and nikic November 20, 2024 13:05

nikic approved these changes Nov 20, 2024

View reviewed changes

paulwalker-arm merged commit 56c091e into llvm:main Nov 21, 2024
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paulwalker-arm deleted the vector-constants-ir-printing branch November 21, 2024 11:37

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[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. #116856

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[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. #116856

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