[AMDGPU][True16][CodeGen] remove v2i16 from srl pattern (#133458)

broxigarchen · web-flow · commit 5bdce305793f · 2025-03-28T18:48:08.000-04:00
remove v2i16 from srl true16 pattern since 16bit right shift on v2i16
should not be applied with this pattern
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2426,9 +2426,8 @@ def : GCNPat <(i1 imm:$imm),
 }
 
 let True16Predicate = UseRealTrue16Insts in
-foreach vt = [i32, v2i16] in
 def : GCNPat <
-  (vt (DivergentBinFrag<srl> VGPR_32:$src, (i32 16))),
+  (i32 (DivergentBinFrag<srl> VGPR_32:$src, (i32 16))),
   (REG_SEQUENCE VGPR_32, (i16 (EXTRACT_SUBREG $src, hi16)), lo16, (V_MOV_B16_t16_e64 0, (i16 0x0000), 0), hi16)
 >;
 

Original file line number	Diff line number	Diff line change
`@@ -2426,9 +2426,8 @@ def : GCNPat <(i1 imm:$imm),`
`2426`	`2426`	`}`
`2427`	`2427`
`2428`	`2428`	`let True16Predicate = UseRealTrue16Insts in`
`2429`		`-foreach vt = [i32, v2i16] in`
`2430`	`2429`	`def : GCNPat <`
`2431`		`- (vt (DivergentBinFrag<srl> VGPR_32:$src, (i32 16))),`
	`2430`	`+ (i32 (DivergentBinFrag<srl> VGPR_32:$src, (i32 16))),`
`2432`	`2431`	`(REG_SEQUENCE VGPR_32, (i16 (EXTRACT_SUBREG $src, hi16)), lo16, (V_MOV_B16_t16_e64 0, (i16 0x0000), 0), hi16)`
`2433`	`2432`	`>;`
`2434`	`2433`