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[AMDGPU][True16][CodeGen] remove v2i16 from srl pattern #133458
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[AMDGPU][True16][CodeGen] remove v2i16 from srl pattern #133458
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@llvm/pr-subscribers-backend-amdgpu Author: Brox Chen (broxigarchen) Changesremove v2i16 from srl true16 pattern since 16bit right shift on v2i16 should not be applied with this pattern Full diff: https://github.com/llvm/llvm-project/pull/133458.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 95797e96aa77e..9051db0c01ed1 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2426,9 +2426,8 @@ def : GCNPat <(i1 imm:$imm),
}
let True16Predicate = UseRealTrue16Insts in
-foreach vt = [i32, v2i16] in
def : GCNPat <
- (vt (DivergentBinFrag<srl> VGPR_32:$src, (i32 16))),
+ (i32 (DivergentBinFrag<srl> VGPR_32:$src, (i32 16))),
(REG_SEQUENCE VGPR_32, (i16 (EXTRACT_SUBREG $src, hi16)), lo16, (V_MOV_B16_t16_e64 0, (i16 0x0000), 0), hi16)
>;
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Makes sense
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/190/builds/17323 Here is the relevant piece of the build log for the reference
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remove v2i16 from srl true16 pattern since 16bit right shift on v2i16 should not be applied with this pattern