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[RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503)
DataLayout, ABI, and TargetLowering can all be obtained via the MachineFunction reference in the State object. This is how the targets that use TableGen for CC handlers get these objects. This might be a little slower, but it simplies all the callers in SelectionDAG and GlobalISel.
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4 files changed

+38
-54
lines changed

4 files changed

+38
-54
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp

Lines changed: 6 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -45,13 +45,8 @@ struct RISCVOutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
4545
CCValAssign::LocInfo LocInfo,
4646
const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
4747
CCState &State) override {
48-
MachineFunction &MF = State.getMachineFunction();
49-
const DataLayout &DL = MF.getDataLayout();
50-
const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
51-
52-
if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
53-
LocInfo, Flags, State, Info.IsFixed, IsRet, Info.Ty,
54-
*Subtarget.getTargetLowering()))
48+
if (RISCVAssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State, Info.IsFixed,
49+
IsRet, Info.Ty))
5550
return true;
5651

5752
StackSize = State.getStackSize();
@@ -197,15 +192,12 @@ struct RISCVIncomingValueAssigner : public CallLowering::IncomingValueAssigner {
197192
const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
198193
CCState &State) override {
199194
MachineFunction &MF = State.getMachineFunction();
200-
const DataLayout &DL = MF.getDataLayout();
201-
const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
202195

203196
if (LocVT.isScalableVector())
204197
MF.getInfo<RISCVMachineFunctionInfo>()->setIsVectorCall();
205198

206-
if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
207-
LocInfo, Flags, State, /*IsFixed=*/true, IsRet, Info.Ty,
208-
*Subtarget.getTargetLowering()))
199+
if (RISCVAssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State,
200+
/*IsFixed=*/true, IsRet, Info.Ty))
209201
return true;
210202

211203
StackSize = State.getStackSize();
@@ -441,11 +433,9 @@ bool RISCVCallLowering::canLowerReturn(MachineFunction &MF,
441433
SmallVectorImpl<BaseArgInfo> &Outs,
442434
bool IsVarArg) const {
443435
SmallVector<CCValAssign, 16> ArgLocs;
444-
const auto &TLI = *getTLI<RISCVTargetLowering>();
445436
CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,
446437
MF.getFunction().getContext());
447438

448-
RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
449439
const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
450440

451441
std::optional<unsigned> FirstMaskArgument = std::nullopt;
@@ -460,9 +450,8 @@ bool RISCVCallLowering::canLowerReturn(MachineFunction &MF,
460450

461451
for (unsigned I = 0, E = Outs.size(); I < E; ++I) {
462452
MVT VT = MVT::getVT(Outs[I].Ty);
463-
if (CC_RISCV(MF.getDataLayout(), ABI, I, VT, VT, CCValAssign::Full,
464-
Outs[I].Flags[0], CCInfo, /*IsFixed=*/true,
465-
/*isRet=*/true, nullptr, TLI))
453+
if (CC_RISCV(I, VT, VT, CCValAssign::Full, Outs[I].Flags[0], CCInfo,
454+
/*IsFixed=*/true, /*isRet=*/true, nullptr))
466455
return false;
467456
}
468457
return true;

‎llvm/lib/Target/RISCV/RISCVCallingConv.cpp

Lines changed: 16 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -247,10 +247,14 @@ static MCRegister allocateRVVReg(MVT ValVT, unsigned ValNo, CCState &State,
247247
}
248248

249249
// Implements the RISC-V calling convention. Returns true upon failure.
250-
bool llvm::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
251-
MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
252-
ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
253-
bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI) {
250+
bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
251+
CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
252+
CCState &State, bool IsFixed, bool IsRet, Type *OrigTy) {
253+
const MachineFunction &MF = State.getMachineFunction();
254+
const DataLayout &DL = MF.getDataLayout();
255+
const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
256+
const RISCVTargetLowering &TLI = *Subtarget.getTargetLowering();
257+
254258
unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
255259
assert(XLen == 32 || XLen == 64);
256260
MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
@@ -276,6 +280,7 @@ bool llvm::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
276280
// variadic argument, or if no F64 argument registers are available.
277281
bool UseGPRForF64 = true;
278282

283+
RISCVABI::ABI ABI = Subtarget.getTargetABI();
279284
switch (ABI) {
280285
default:
281286
llvm_unreachable("Unexpected ABI");
@@ -502,21 +507,22 @@ bool llvm::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
502507

503508
// FastCC has less than 1% performance improvement for some particular
504509
// benchmark. But theoretically, it may have benefit for some cases.
505-
bool llvm::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
506-
unsigned ValNo, MVT ValVT, MVT LocVT,
510+
bool llvm::CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT,
507511
CCValAssign::LocInfo LocInfo,
508512
ISD::ArgFlagsTy ArgFlags, CCState &State,
509-
bool IsFixed, bool IsRet, Type *OrigTy,
510-
const RISCVTargetLowering &TLI) {
513+
bool IsFixed, bool IsRet, Type *OrigTy) {
514+
const MachineFunction &MF = State.getMachineFunction();
515+
const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
516+
const RISCVTargetLowering &TLI = *Subtarget.getTargetLowering();
517+
RISCVABI::ABI ABI = Subtarget.getTargetABI();
518+
511519
if (LocVT == MVT::i32 || LocVT == MVT::i64) {
512520
if (MCRegister Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
513521
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
514522
return false;
515523
}
516524
}
517525

518-
const RISCVSubtarget &Subtarget = TLI.getSubtarget();
519-
520526
if (LocVT == MVT::f16 && Subtarget.hasStdExtZfhmin()) {
521527
static const MCPhysReg FPR16List[] = {
522528
RISCV::F10_H, RISCV::F11_H, RISCV::F12_H, RISCV::F13_H, RISCV::F14_H,

‎llvm/lib/Target/RISCV/RISCVCallingConv.h

Lines changed: 10 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -15,28 +15,21 @@
1515

1616
namespace llvm {
1717

18-
class DataLayout;
19-
class RISCVTargetLowering;
20-
2118
/// RISCVCCAssignFn - This target-specific function extends the default
2219
/// CCValAssign with additional information used to lower RISC-V calling
2320
/// conventions.
24-
typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI,
25-
unsigned ValNo, MVT ValVT, MVT LocVT,
21+
typedef bool RISCVCCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT,
2622
CCValAssign::LocInfo LocInfo,
2723
ISD::ArgFlagsTy ArgFlags, CCState &State,
28-
bool IsFixed, bool IsRet, Type *OrigTy,
29-
const RISCVTargetLowering &TLI);
30-
31-
bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
32-
MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
33-
ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
34-
bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI);
35-
36-
bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
37-
MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
38-
ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
39-
bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI);
24+
bool IsFixed, bool IsRet, Type *OrigTy);
25+
26+
bool CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
27+
CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
28+
CCState &State, bool IsFixed, bool IsRet, Type *OrigTy);
29+
30+
bool CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT,
31+
CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
32+
CCState &State, bool IsFixed, bool IsRet, Type *OrigTy);
4033

4134
bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
4235
CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 6 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -18951,9 +18951,8 @@ void RISCVTargetLowering::analyzeInputArgs(
1895118951
else if (Ins[i].isOrigArg())
1895218952
ArgTy = FType->getParamType(Ins[i].getOrigArgIndex());
1895318953

18954-
RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
18955-
if (Fn(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full,
18956-
ArgFlags, CCInfo, /*IsFixed=*/true, IsRet, ArgTy, *this)) {
18954+
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo,
18955+
/*IsFixed=*/true, IsRet, ArgTy)) {
1895718956
LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type "
1895818957
<< ArgVT << '\n');
1895918958
llvm_unreachable(nullptr);
@@ -18972,9 +18971,8 @@ void RISCVTargetLowering::analyzeOutputArgs(
1897218971
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
1897318972
Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty : nullptr;
1897418973

18975-
RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
18976-
if (Fn(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full,
18977-
ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy, *this)) {
18974+
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo,
18975+
Outs[i].IsFixed, IsRet, OrigTy)) {
1897818976
LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type "
1897918977
<< ArgVT << "\n");
1898018978
llvm_unreachable(nullptr);
@@ -19688,10 +19686,8 @@ bool RISCVTargetLowering::CanLowerReturn(
1968819686
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
1968919687
MVT VT = Outs[i].VT;
1969019688
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
19691-
RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
19692-
if (CC_RISCV(MF.getDataLayout(), ABI, i, VT, VT, CCValAssign::Full,
19693-
ArgFlags, CCInfo, /*IsFixed=*/true, /*IsRet=*/true, nullptr,
19694-
*this))
19689+
if (CC_RISCV(i, VT, VT, CCValAssign::Full, ArgFlags, CCInfo,
19690+
/*IsFixed=*/true, /*IsRet=*/true, nullptr))
1969519691
return false;
1969619692
}
1969719693
return true;

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