[RISCV] Reduce the interface to RISCVCCAssignFn. NFC #107503
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DataLayout, ABI, and TargetLowering can all be obtained via the MachineFunction reference in the State object. This is how the targets that use TableGen for CC handlers get these objects. This might be a little slower, but it simplies all the callers in SelectionDAG and GlobalISel.
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesDataLayout, ABI, and TargetLowering can all be obtained via the MachineFunction reference in the State object. This is how the targets that use TableGen for CC handlers get these objects. This might be a little slower, but it simplies all the callers in SelectionDAG and GlobalISel. Full diff: https://github.com/llvm/llvm-project/pull/107503.diff 3 Files Affected:
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
index 31a9df53a2aa1b..cb2922293922c0 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -45,13 +45,8 @@ struct RISCVOutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
CCValAssign::LocInfo LocInfo,
const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
CCState &State) override {
- MachineFunction &MF = State.getMachineFunction();
- const DataLayout &DL = MF.getDataLayout();
- const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
-
- if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
- LocInfo, Flags, State, Info.IsFixed, IsRet, Info.Ty,
- *Subtarget.getTargetLowering()))
+ if (RISCVAssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State, Info.IsFixed,
+ IsRet, Info.Ty))
return true;
StackSize = State.getStackSize();
@@ -198,15 +193,12 @@ struct RISCVIncomingValueAssigner : public CallLowering::IncomingValueAssigner {
const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
CCState &State) override {
MachineFunction &MF = State.getMachineFunction();
- const DataLayout &DL = MF.getDataLayout();
- const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
if (LocVT.isScalableVector())
MF.getInfo<RISCVMachineFunctionInfo>()->setIsVectorCall();
- if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
- LocInfo, Flags, State, /*IsFixed=*/true, IsRet, Info.Ty,
- *Subtarget.getTargetLowering()))
+ if (RISCVAssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State,
+ /*IsFixed=*/true, IsRet, Info.Ty))
return true;
StackSize = State.getStackSize();
@@ -446,7 +438,6 @@ bool RISCVCallLowering::canLowerReturn(MachineFunction &MF,
CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,
MF.getFunction().getContext());
- RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
std::optional<unsigned> FirstMaskArgument = std::nullopt;
@@ -461,9 +452,9 @@ bool RISCVCallLowering::canLowerReturn(MachineFunction &MF,
for (unsigned I = 0, E = Outs.size(); I < E; ++I) {
MVT VT = MVT::getVT(Outs[I].Ty);
- if (RISCV::CC_RISCV(MF.getDataLayout(), ABI, I, VT, VT, CCValAssign::Full,
- Outs[I].Flags[0], CCInfo, /*IsFixed=*/true,
- /*isRet=*/true, nullptr, TLI))
+ if (RISCV::CC_RISCV(I, VT, VT, CCValAssign::Full, Outs[I].Flags[0], CCInfo,
+ /*IsFixed=*/true,
+ /*isRet=*/true, nullptr))
return false;
}
return true;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 6b4219b4623847..33c86c98c8cbfb 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -19167,10 +19167,14 @@ static MCRegister allocateRVVReg(MVT ValVT, unsigned ValNo, CCState &State,
}
// Implements the RISC-V calling convention. Returns true upon failure.
-bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
- MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
- ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
- bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI) {
+bool RISCV::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
+ CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
+ CCState &State, bool IsFixed, bool IsRet, Type *OrigTy) {
+ const MachineFunction &MF = State.getMachineFunction();
+ const DataLayout &DL = MF.getDataLayout();
+ const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
+ const RISCVTargetLowering &TLI = *STI.getTargetLowering();
+
unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
assert(XLen == 32 || XLen == 64);
MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
@@ -19196,6 +19200,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
// variadic argument, or if no F64 argument registers are available.
bool UseGPRForF64 = true;
+ RISCVABI::ABI ABI = STI.getTargetABI();
switch (ABI) {
default:
llvm_unreachable("Unexpected ABI");
@@ -19437,9 +19442,8 @@ void RISCVTargetLowering::analyzeInputArgs(
else if (Ins[i].isOrigArg())
ArgTy = FType->getParamType(Ins[i].getOrigArgIndex());
- RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
- if (Fn(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full,
- ArgFlags, CCInfo, /*IsFixed=*/true, IsRet, ArgTy, *this)) {
+ if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo,
+ /*IsFixed=*/true, IsRet, ArgTy)) {
LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type "
<< ArgVT << '\n');
llvm_unreachable(nullptr);
@@ -19458,9 +19462,8 @@ void RISCVTargetLowering::analyzeOutputArgs(
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty : nullptr;
- RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
- if (Fn(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full,
- ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy, *this)) {
+ if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo,
+ Outs[i].IsFixed, IsRet, OrigTy)) {
LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type "
<< ArgVT << "\n");
llvm_unreachable(nullptr);
@@ -19633,12 +19636,15 @@ static SDValue unpackF64OnRV32DSoftABI(SelectionDAG &DAG, SDValue Chain,
// FastCC has less than 1% performance improvement for some particular
// benchmark. But theoretically, it may have benefit for some cases.
-bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
- unsigned ValNo, MVT ValVT, MVT LocVT,
+bool RISCV::CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State,
- bool IsFixed, bool IsRet, Type *OrigTy,
- const RISCVTargetLowering &TLI) {
+ bool IsFixed, bool IsRet, Type *OrigTy) {
+ const MachineFunction &MF = State.getMachineFunction();
+ const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
+ const RISCVTargetLowering &TLI = *STI.getTargetLowering();
+ RISCVABI::ABI ABI = STI.getTargetABI();
+
if (LocVT == MVT::i32 || LocVT == MVT::i64) {
if (MCRegister Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
@@ -20357,10 +20363,8 @@ bool RISCVTargetLowering::CanLowerReturn(
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
MVT VT = Outs[i].VT;
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
- RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
- if (RISCV::CC_RISCV(MF.getDataLayout(), ABI, i, VT, VT, CCValAssign::Full,
- ArgFlags, CCInfo, /*IsFixed=*/true, /*IsRet=*/true,
- nullptr, *this))
+ if (RISCV::CC_RISCV(i, VT, VT, CCValAssign::Full, ArgFlags, CCInfo,
+ /*IsFixed=*/true, /*IsRet=*/true, nullptr))
return false;
}
return true;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 3beee4686956ec..ee25d760a2919b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -899,12 +899,10 @@ class RISCVTargetLowering : public TargetLowering {
/// RISCVCCAssignFn - This target-specific function extends the default
/// CCValAssign with additional information used to lower RISC-V calling
/// conventions.
- typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI,
- unsigned ValNo, MVT ValVT, MVT LocVT,
+ typedef bool RISCVCCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State,
- bool IsFixed, bool IsRet, Type *OrigTy,
- const RISCVTargetLowering &TLI);
+ bool IsFixed, bool IsRet, Type *OrigTy);
private:
void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
@@ -1050,15 +1048,13 @@ class RISCVTargetLowering : public TargetLowering {
namespace RISCV {
-bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
- MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
- ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
- bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI);
+bool CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
+ CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
+ CCState &State, bool IsFixed, bool IsRet, Type *OrigTy);
-bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
- MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
- ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
- bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI);
+bool CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT,
+ CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
+ CCState &State, bool IsFixed, bool IsRet, Type *OrigTy);
bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
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wangpc-pp
approved these changes
Sep 6, 2024
Yes. I wasn't sure which would be accepted so I didn't make the dependent. Should be pretty simple rebases. |
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DataLayout, ABI, and TargetLowering can all be obtained via the MachineFunction reference in the State object. This is how the targets that use TableGen for CC handlers get these objects.
This might be a little slower, but it simplies all the callers in SelectionDAG and GlobalISel.