Remove v1f64

If we set v1f64 as legal, FMINNUM/FMAXNUM will have some problem:
   both of them use `if (isOperationLegalOrCustom(FMAXNUM_IEEE, VT))`.

AArch64 depends on `expandFMINNUM_FMAXNUM` returning `SDValue()`
for FMAXNUM and FMINNUM.

We should fix this problem, while it will be in future patch.

Author: wzssyqa

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -1196,6 +1196,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
           ISD::FEXP10,            ISD::FRINT,          ISD::FROUND,
           ISD::FROUNDEVEN,        ISD::FTRUNC,         ISD::FMINNUM,
           ISD::FMAXNUM,           ISD::FMINIMUM,       ISD::FMAXIMUM,
+          ISD::FMAXNUM_IEEE,      ISD::FMINNUM_IEEE,
           ISD::STRICT_FADD,       ISD::STRICT_FSUB,    ISD::STRICT_FMUL,
           ISD::STRICT_FDIV,       ISD::STRICT_FMA,     ISD::STRICT_FCEIL,
           ISD::STRICT_FFLOOR,     ISD::STRICT_FSQRT,   ISD::STRICT_FRINT,
@@ -1205,9 +1206,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setOperationAction(Op, MVT::v1f64, Expand);
     // clang-format on
 
-    for (auto Op : {ISD::FMAXNUM_IEEE, ISD::FMINNUM_IEEE})
-      setOperationAction(Op, MVT::v1f64, Legal);
-
     for (auto Op :
          {ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::SINT_TO_FP, ISD::UINT_TO_FP,
           ISD::FP_ROUND, ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, ISD::MUL,
@@ -1938,10 +1936,10 @@ void AArch64TargetLowering::addTypeForNEON(MVT VT) {
       (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()))
     for (unsigned Opcode :
          {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM,
-          ISD::STRICT_FMINIMUM, ISD::STRICT_FMAXIMUM, ISD::STRICT_FMINNUM,
-          ISD::STRICT_FMAXNUM, ISD::STRICT_FADD, ISD::STRICT_FSUB,
-          ISD::STRICT_FMUL, ISD::STRICT_FDIV, ISD::STRICT_FMA,
-          ISD::STRICT_FSQRT})
+          ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE, ISD::STRICT_FMINIMUM,
+          ISD::STRICT_FMAXIMUM, ISD::STRICT_FMINNUM, ISD::STRICT_FMAXNUM,
+          ISD::STRICT_FADD, ISD::STRICT_FSUB, ISD::STRICT_FMUL,
+          ISD::STRICT_FDIV, ISD::STRICT_FMA, ISD::STRICT_FSQRT})
       setOperationAction(Opcode, VT, Legal);
 
   // Strict fp extend and trunc are legal

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -5071,10 +5071,6 @@ def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
 def : Pat<(v1f64 (fminnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
           (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
 
-def : Pat<(v1f64 (fmaxnum_ieee (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
-          (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
-def : Pat<(v1f64 (fminnum_ieee (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
-          (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
 def : Pat<(fminnum_ieee (f64 FPR64:$a), (f64 FPR64:$b)),
           (FMINNMDrr FPR64:$a, FPR64:$b)>;
 def : Pat<(fminnum_ieee (f32 FPR32:$a), (f32 FPR32:$b)),

llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll

@@ -32,16 +32,6 @@ entry:
   ret <8 x half> %c
 }
 
-define <1 x double> @max_v1f64(<1 x double> %a, <1 x double> %b) {
-; AARCH64-LABEL: max_v1f64:
-; AARCH64:       // %bb.0: // %entry
-; AARCH64-NEXT:    fmaxnm d0, d0, d1
-; AARCH64-NEXT:    ret
-entry:
-  %c = call nnan <1 x double> @llvm.maximumnum.v1f64(<1 x double> %a, <1 x double> %b)
-  ret <1 x double> %c
-}
-
 define double @max_f64(double %a, double %b) {
 ; AARCH64-LABEL: max_f64:
 ; AARCH64:       // %bb.0: // %entry
@@ -103,16 +93,6 @@ entry:
   ret <8 x half> %c
 }
 
-define <1 x double> @min_v1f64(<1 x double> %a, <1 x double> %b) {
-; AARCH64-LABEL: min_v1f64:
-; AARCH64:       // %bb.0: // %entry
-; AARCH64-NEXT:    fminnm d0, d0, d1
-; AARCH64-NEXT:    ret
-entry:
-  %c = call nnan <1 x double> @llvm.minimumnum.v1f64(<1 x double> %a, <1 x double> %b)
-  ret <1 x double> %c
-}
-
 define double @min_f64(double %a, double %b) {
 ; AARCH64-LABEL: min_f64:
 ; AARCH64:       // %bb.0: // %entry