Clean up vector type creation

Author: SamTebbs33

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

@@ -1791,21 +1791,17 @@ SDValue VectorLegalizer::ExpandLOOP_DEPENDENCE_MASK(SDNode *N) {
   Diff = DAG.getNode(ISD::SDIV, DL, PtrVT, Diff, EltSize);
 
   // If the difference is positive then some elements may alias
-  auto CmpVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
-                                      Diff.getValueType());
+  EVT CmpVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
+                                     Diff.getValueType());
   SDValue Zero = DAG.getTargetConstant(0, DL, PtrVT);
   SDValue Cmp = DAG.getSetCC(DL, CmpVT, Diff, Zero,
                              IsReadAfterWrite ? ISD::SETEQ : ISD::SETLE);
 
   // Create the lane mask
-  EVT SplatTY =
-      EVT::getVectorVT(*DAG.getContext(), PtrVT, VT.getVectorMinNumElements(),
-                       VT.isScalableVector());
+  EVT SplatTY = VT.changeElementType(PtrVT);
   SDValue DiffSplat = DAG.getSplat(SplatTY, DL, Diff);
   SDValue VectorStep = DAG.getStepVector(DL, SplatTY);
-  EVT MaskVT =
-      EVT::getVectorVT(*DAG.getContext(), MVT::i1, VT.getVectorMinNumElements(),
-                       VT.isScalableVector());
+  EVT MaskVT = VT.changeElementType(MVT::i1);
   SDValue DiffMask =
       DAG.getSetCC(DL, MaskVT, VectorStep, DiffSplat, ISD::CondCode::SETULT);
 

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

@@ -8247,7 +8247,6 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
   case Intrinsic::loop_dependence_war_mask:
   case Intrinsic::loop_dependence_raw_mask: {
     auto IntrinsicVT = EVT::getEVT(I.getType());
-    SmallVector<SDValue, 4> Ops;
     unsigned ID = Intrinsic == Intrinsic::loop_dependence_war_mask
                       ? ISD::LOOP_DEPENDENCE_WAR_MASK
                       : ISD::LOOP_DEPENDENCE_RAW_MASK;

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -6390,7 +6390,8 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     return DAG.getNode(AArch64ISD::USDOT, dl, Op.getValueType(),
                        Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
   }
-  case Intrinsic::experimental_get_nonalias_lane_mask: {
+  case Intrinsic::loop_dependence_war_mask:
+  case Intrinsic::loop_dependence_raw_mask: {
     unsigned IntrinsicID = 0;
     uint64_t EltSize = Op.getOperand(3)->getAsZExtVal();
     bool IsWriteAfterRead = Op.getOperand(4)->getAsZExtVal() == 1;
@@ -19643,9 +19644,9 @@ static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op,
                         AArch64CC::CondCode Cond);
 
 static bool isPredicateCCSettingOp(SDValue N) {
-  if ((N.getOpcode() == ISD::SETCC ||
-       // get_active_lane_mask is lowered to a whilelo instruction.
-       N.getOpcode() == ISD::GET_ACTIVE_LANE_MASK) ||
+  if ((N.getOpcode() == ISD::SETCC) ||
+      // get_active_lane_mask is lowered to a whilelo instruction.
+      (N.getOpcode() == ISD::GET_ACTIVE_LANE_MASK) ||
       (N.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
        (N.getConstantOperandVal(0) == Intrinsic::aarch64_sve_whilege ||
         N.getConstantOperandVal(0) == Intrinsic::aarch64_sve_whilegt ||