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Remove experimental from intrinsic name
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12 files changed

+68
-74
lines changed

12 files changed

+68
-74
lines changed

‎llvm/docs/LangRef.rst

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -23970,9 +23970,9 @@ Examples:
2397023970
%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %3, i32 4, <4 x i1> %active.lane.mask, <4 x i32> poison)
2397123971

2397223972

23973-
.. _int_experimental_loop_dependence_war_mask:
23973+
.. _int_loop_dependence_war_mask:
2397423974

23975-
'``llvm.experimental.loop.dependence.war.mask.*``' Intrinsics
23975+
'``llvm.loop.dependence.war.mask.*``' Intrinsics
2397623976
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2397723977

2397823978
Syntax:
@@ -23981,10 +23981,10 @@ This is an overloaded intrinsic.
2398123981

2398223982
::
2398323983

23984-
declare <4 x i1> @llvm.experimental.loop.dependence.war.mask.v4i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
23985-
declare <8 x i1> @llvm.experimental.loop.dependence.war.mask.v8i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
23986-
declare <16 x i1> @llvm.experimental.loop.dependence.war.mask.v16i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
23987-
declare <vscale x 16 x i1> @llvm.experimental.loop.dependence.war.mask.nxv16i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
23984+
declare <4 x i1> @llvm.loop.dependence.war.mask.v4i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
23985+
declare <8 x i1> @llvm.loop.dependence.war.mask.v8i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
23986+
declare <16 x i1> @llvm.loop.dependence.war.mask.v16i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
23987+
declare <vscale x 16 x i1> @llvm.loop.dependence.war.mask.nxv16i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
2398823988

2398923989

2399023990
Overview:
@@ -24024,14 +24024,14 @@ Examples:
2402424024

2402524025
.. code-block:: llvm
2402624026

24027-
%loop.dependence.mask = call <4 x i1> @llvm.experimental.loop.dependence.war.mask.v4i1(ptr %ptrA, ptr %ptrB, i64 4)
24027+
%loop.dependence.mask = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1(ptr %ptrA, ptr %ptrB, i64 4)
2402824028
%vecA = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(ptr %ptrA, i32 4, <4 x i1> %loop.dependence.mask, <4 x i32> poison)
2402924029
[...]
2403024030
call @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %vecA, ptr %ptrB, i32 4, <4 x i1> %loop.dependence.mask)
2403124031

24032-
.. _int_experimental_loop_dependence_raw_mask:
24032+
.. _int_loop_dependence_raw_mask:
2403324033

24034-
'``llvm.experimental.loop.dependence.raw.mask.*``' Intrinsics
24034+
'``llvm.loop.dependence.raw.mask.*``' Intrinsics
2403524035
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2403624036

2403724037
Syntax:
@@ -24040,10 +24040,10 @@ This is an overloaded intrinsic.
2404024040

2404124041
::
2404224042

24043-
declare <4 x i1> @llvm.experimental.loop.dependence.raw.mask.v4i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
24044-
declare <8 x i1> @llvm.experimental.loop.dependence.raw.mask.v8i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
24045-
declare <16 x i1> @llvm.experimental.loop.dependence.raw.mask.v16i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
24046-
declare <vscale x 16 x i1> @llvm.experimental.loop.dependence.raw.mask.nxv16i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
24043+
declare <4 x i1> @llvm.loop.dependence.raw.mask.v4i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
24044+
declare <8 x i1> @llvm.loop.dependence.raw.mask.v8i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
24045+
declare <16 x i1> @llvm.loop.dependence.raw.mask.v16i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
24046+
declare <vscale x 16 x i1> @llvm.loop.dependence.raw.mask.nxv16i1(ptr %ptrA, ptr %ptrB, i64 immarg %elementSize)
2404724047

2404824048

2404924049
Overview:
@@ -24086,7 +24086,7 @@ Examples:
2408624086

2408724087
.. code-block:: llvm
2408824088

24089-
%loop.dependence.mask = call <4 x i1> @llvm.experimental.loop.dependence.raw.mask.v4i1(ptr %ptrA, ptr %ptrB, i64 4)
24089+
%loop.dependence.mask = call <4 x i1> @llvm.loop.dependence.raw.mask.v4i1(ptr %ptrA, ptr %ptrB, i64 4)
2409024090
call @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %vecA, ptr %ptrA, i32 4, <4 x i1> %loop.dependence.mask)
2409124091
[...]
2409224092
%vecB = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(ptr %ptrB, i32 4, <4 x i1> %loop.dependence.mask, <4 x i32> poison)

‎llvm/include/llvm/CodeGen/ISDOpcodes.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1559,8 +1559,8 @@ enum NodeType {
15591559
// The `llvm.experimental.loop.dependence.{war, raw}.mask` intrinsics
15601560
// Operands: Load pointer, Store pointer, Element size
15611561
// Output: Mask
1562-
EXPERIMENTAL_LOOP_DEPENDENCE_WAR_MASK,
1563-
EXPERIMENTAL_LOOP_DEPENDENCE_RAW_MASK,
1562+
LOOP_DEPENDENCE_WAR_MASK,
1563+
LOOP_DEPENDENCE_RAW_MASK,
15641564

15651565
// llvm.clear_cache intrinsic
15661566
// Operands: Input Chain, Start Addres, End Address

‎llvm/include/llvm/IR/Intrinsics.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2399,12 +2399,12 @@ let IntrProperties = [IntrNoMem, ImmArg<ArgIndex<1>>] in {
23992399
llvm_i32_ty]>;
24002400
}
24012401

2402-
def int_experimental_loop_dependence_raw_mask:
2402+
def int_loop_dependence_raw_mask:
24032403
DefaultAttrsIntrinsic<[llvm_anyvector_ty],
24042404
[llvm_ptr_ty, llvm_ptr_ty, llvm_i64_ty],
24052405
[IntrNoMem, IntrNoSync, IntrWillReturn, ImmArg<ArgIndex<2>>]>;
24062406

2407-
def int_experimental_loop_dependence_war_mask:
2407+
def int_loop_dependence_war_mask:
24082408
DefaultAttrsIntrinsic<[llvm_anyvector_ty],
24092409
[llvm_ptr_ty, llvm_ptr_ty, llvm_i64_ty],
24102410
[IntrNoMem, IntrNoSync, IntrWillReturn, ImmArg<ArgIndex<2>>]>;

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -322,9 +322,9 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
322322
Res = PromoteIntRes_VP_REDUCE(N);
323323
break;
324324

325-
case ISD::EXPERIMENTAL_LOOP_DEPENDENCE_WAR_MASK:
326-
case ISD::EXPERIMENTAL_LOOP_DEPENDENCE_RAW_MASK:
327-
Res = PromoteIntRes_EXPERIMENTAL_LOOP_DEPENDENCE_MASK(N);
325+
case ISD::LOOP_DEPENDENCE_WAR_MASK:
326+
case ISD::LOOP_DEPENDENCE_RAW_MASK:
327+
Res = PromoteIntRes_LOOP_DEPENDENCE_MASK(N);
328328
break;
329329

330330
case ISD::FREEZE:
@@ -374,8 +374,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
374374
return GetPromotedInteger(Op);
375375
}
376376

377-
SDValue
378-
DAGTypeLegalizer::PromoteIntRes_EXPERIMENTAL_LOOP_DEPENDENCE_MASK(SDNode *N) {
377+
SDValue DAGTypeLegalizer::PromoteIntRes_LOOP_DEPENDENCE_MASK(SDNode *N) {
379378
EVT VT = N->getValueType(0);
380379
EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
381380
return DAG.getNode(N->getOpcode(), SDLoc(N), NewVT, N->ops());
@@ -2107,9 +2106,9 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
21072106
case ISD::PARTIAL_REDUCE_SMLA:
21082107
Res = PromoteIntOp_PARTIAL_REDUCE_MLA(N);
21092108
break;
2110-
case ISD::EXPERIMENTAL_LOOP_DEPENDENCE_RAW_MASK:
2111-
case ISD::EXPERIMENTAL_LOOP_DEPENDENCE_WAR_MASK:
2112-
Res = PromoteIntOp_EXPERIMENTAL_LOOP_DEPENDENCE_MASK(N, OpNo);
2109+
case ISD::LOOP_DEPENDENCE_RAW_MASK:
2110+
case ISD::LOOP_DEPENDENCE_WAR_MASK:
2111+
Res = PromoteIntOp_LOOP_DEPENDENCE_MASK(N, OpNo);
21132112
break;
21142113
}
21152114

@@ -2912,8 +2911,8 @@ SDValue DAGTypeLegalizer::PromoteIntOp_PARTIAL_REDUCE_MLA(SDNode *N) {
29122911
return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
29132912
}
29142913

2915-
SDValue DAGTypeLegalizer::PromoteIntOp_EXPERIMENTAL_LOOP_DEPENDENCE_MASK(
2916-
SDNode *N, unsigned OpNo) {
2914+
SDValue DAGTypeLegalizer::PromoteIntOp_LOOP_DEPENDENCE_MASK(SDNode *N,
2915+
unsigned OpNo) {
29172916
SmallVector<SDValue, 4> NewOps(N->ops());
29182917
NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
29192918
return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -381,7 +381,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
381381
SDValue PromoteIntRes_VECTOR_FIND_LAST_ACTIVE(SDNode *N);
382382
SDValue PromoteIntRes_GET_ACTIVE_LANE_MASK(SDNode *N);
383383
SDValue PromoteIntRes_PARTIAL_REDUCE_MLA(SDNode *N);
384-
SDValue PromoteIntRes_EXPERIMENTAL_LOOP_DEPENDENCE_MASK(SDNode *N);
384+
SDValue PromoteIntRes_LOOP_DEPENDENCE_MASK(SDNode *N);
385385

386386
// Integer Operand Promotion.
387387
bool PromoteIntegerOperand(SDNode *N, unsigned OpNo);
@@ -435,8 +435,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
435435
SDValue PromoteIntOp_VECTOR_FIND_LAST_ACTIVE(SDNode *N, unsigned OpNo);
436436
SDValue PromoteIntOp_GET_ACTIVE_LANE_MASK(SDNode *N);
437437
SDValue PromoteIntOp_PARTIAL_REDUCE_MLA(SDNode *N);
438-
SDValue PromoteIntOp_EXPERIMENTAL_LOOP_DEPENDENCE_MASK(SDNode *N,
439-
unsigned OpNo);
438+
SDValue PromoteIntOp_LOOP_DEPENDENCE_MASK(SDNode *N, unsigned OpNo);
440439

441440
void SExtOrZExtPromotedOperands(SDValue &LHS, SDValue &RHS);
442441
void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -470,8 +470,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
470470
case ISD::VECTOR_COMPRESS:
471471
case ISD::SCMP:
472472
case ISD::UCMP:
473-
case ISD::EXPERIMENTAL_LOOP_DEPENDENCE_WAR_MASK:
474-
case ISD::EXPERIMENTAL_LOOP_DEPENDENCE_RAW_MASK:
473+
case ISD::LOOP_DEPENDENCE_WAR_MASK:
474+
case ISD::LOOP_DEPENDENCE_RAW_MASK:
475475
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
476476
break;
477477
case ISD::SMULFIX:
@@ -1265,8 +1265,8 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
12651265
case ISD::UCMP:
12661266
Results.push_back(TLI.expandCMP(Node, DAG));
12671267
return;
1268-
case ISD::EXPERIMENTAL_LOOP_DEPENDENCE_WAR_MASK:
1269-
case ISD::EXPERIMENTAL_LOOP_DEPENDENCE_RAW_MASK:
1268+
case ISD::LOOP_DEPENDENCE_WAR_MASK:
1269+
case ISD::LOOP_DEPENDENCE_RAW_MASK:
12701270
Results.push_back(ExpandLOOP_DEPENDENCE_MASK(Node));
12711271
return;
12721272

@@ -1780,8 +1780,7 @@ SDValue VectorLegalizer::ExpandLOOP_DEPENDENCE_MASK(SDNode *N) {
17801780
SDValue SinkValue = N->getOperand(1);
17811781
SDValue EltSize = N->getOperand(2);
17821782

1783-
bool IsReadAfterWrite =
1784-
N->getOpcode() == ISD::EXPERIMENTAL_LOOP_DEPENDENCE_RAW_MASK;
1783+
bool IsReadAfterWrite = N->getOpcode() == ISD::LOOP_DEPENDENCE_RAW_MASK;
17851784
auto VT = N->getValueType(0);
17861785
auto PtrVT = SourceValue->getValueType(0);
17871786

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8244,13 +8244,13 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
82448244
visitVectorExtractLastActive(I, Intrinsic);
82458245
return;
82468246
}
8247-
case Intrinsic::experimental_loop_dependence_war_mask:
8248-
case Intrinsic::experimental_loop_dependence_raw_mask: {
8247+
case Intrinsic::loop_dependence_war_mask:
8248+
case Intrinsic::loop_dependence_raw_mask: {
82498249
auto IntrinsicVT = EVT::getEVT(I.getType());
82508250
SmallVector<SDValue, 4> Ops;
8251-
unsigned ID = Intrinsic == Intrinsic::experimental_loop_dependence_war_mask
8252-
? ISD::EXPERIMENTAL_LOOP_DEPENDENCE_WAR_MASK
8253-
: ISD::EXPERIMENTAL_LOOP_DEPENDENCE_RAW_MASK;
8251+
unsigned ID = Intrinsic == Intrinsic::loop_dependence_war_mask
8252+
? ISD::LOOP_DEPENDENCE_WAR_MASK
8253+
: ISD::LOOP_DEPENDENCE_RAW_MASK;
82548254
setValue(&I,
82558255
DAG.getNode(ID, sdl, IntrinsicVT, getValue(I.getOperand(0)),
82568256
getValue(I.getOperand(1)), getValue(I.getOperand(2))));

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -585,9 +585,9 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
585585
return "partial_reduce_umla";
586586
case ISD::PARTIAL_REDUCE_SMLA:
587587
return "partial_reduce_smla";
588-
case ISD::EXPERIMENTAL_LOOP_DEPENDENCE_WAR_MASK:
588+
case ISD::LOOP_DEPENDENCE_WAR_MASK:
589589
return "loop_dep_war";
590-
case ISD::EXPERIMENTAL_LOOP_DEPENDENCE_RAW_MASK:
590+
case ISD::LOOP_DEPENDENCE_RAW_MASK:
591591
return "loop_dep_raw";
592592

593593
// Vector Predication

‎llvm/lib/CodeGen/TargetLoweringBase.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -840,8 +840,8 @@ void TargetLoweringBase::initActions() {
840840
setOperationAction(ISD::VECTOR_FIND_LAST_ACTIVE, VT, Expand);
841841

842842
// Lane mask with non-aliasing lanes enabled default to expand
843-
setOperationAction(ISD::EXPERIMENTAL_LOOP_DEPENDENCE_RAW_MASK, VT, Expand);
844-
setOperationAction(ISD::EXPERIMENTAL_LOOP_DEPENDENCE_WAR_MASK, VT, Expand);
843+
setOperationAction(ISD::LOOP_DEPENDENCE_RAW_MASK, VT, Expand);
844+
setOperationAction(ISD::LOOP_DEPENDENCE_WAR_MASK, VT, Expand);
845845

846846
// FP environment operations default to expand.
847847
setOperationAction(ISD::GET_FPENV, VT, Expand);

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1904,10 +1904,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
19041904
(Subtarget->hasSME() && Subtarget->isStreaming())) {
19051905
for (auto VT : {MVT::v2i32, MVT::v4i16, MVT::v8i8, MVT::v16i8, MVT::nxv2i1,
19061906
MVT::nxv4i1, MVT::nxv8i1, MVT::nxv16i1}) {
1907-
setOperationAction(ISD::EXPERIMENTAL_LOOP_DEPENDENCE_RAW_MASK, VT,
1908-
Custom);
1909-
setOperationAction(ISD::EXPERIMENTAL_LOOP_DEPENDENCE_WAR_MASK, VT,
1910-
Custom);
1907+
setOperationAction(ISD::LOOP_DEPENDENCE_RAW_MASK, VT, Custom);
1908+
setOperationAction(ISD::LOOP_DEPENDENCE_WAR_MASK, VT, Custom);
19111909
}
19121910
}
19131911

@@ -5101,8 +5099,7 @@ AArch64TargetLowering::LowerLOOP_DEPENDENCE_MASK(SDValue Op,
51015099
SelectionDAG &DAG) const {
51025100
SDLoc DL(Op);
51035101
uint64_t EltSize = Op.getConstantOperandVal(2);
5104-
bool IsWriteAfterRead =
5105-
Op.getOpcode() == ISD::EXPERIMENTAL_LOOP_DEPENDENCE_WAR_MASK;
5102+
bool IsWriteAfterRead = Op.getOpcode() == ISD::LOOP_DEPENDENCE_WAR_MASK;
51065103
unsigned Opcode =
51075104
IsWriteAfterRead ? AArch64ISD::WHILEWR : AArch64ISD::WHILERW;
51085105
EVT VT = Op.getValueType();
@@ -7302,8 +7299,8 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
73027299
default:
73037300
llvm_unreachable("unimplemented operand");
73047301
return SDValue();
7305-
case ISD::EXPERIMENTAL_LOOP_DEPENDENCE_RAW_MASK:
7306-
case ISD::EXPERIMENTAL_LOOP_DEPENDENCE_WAR_MASK:
7302+
case ISD::LOOP_DEPENDENCE_RAW_MASK:
7303+
case ISD::LOOP_DEPENDENCE_WAR_MASK:
73077304
return LowerLOOP_DEPENDENCE_MASK(Op, DAG);
73087305
case ISD::BITCAST:
73097306
return LowerBITCAST(Op, DAG);
@@ -27606,8 +27603,8 @@ void AArch64TargetLowering::ReplaceNodeResults(
2760627603
// CONCAT_VECTORS -- but delegate to common code for result type
2760727604
// legalisation
2760827605
return;
27609-
case ISD::EXPERIMENTAL_LOOP_DEPENDENCE_WAR_MASK:
27610-
case ISD::EXPERIMENTAL_LOOP_DEPENDENCE_RAW_MASK: {
27606+
case ISD::LOOP_DEPENDENCE_WAR_MASK:
27607+
case ISD::LOOP_DEPENDENCE_RAW_MASK: {
2761127608
EVT VT = N->getValueType(0);
2761227609
if (!VT.isFixedLengthVector() || VT.getVectorElementType() != MVT::i1)
2761327610
return;
@@ -27678,8 +27675,8 @@ void AArch64TargetLowering::ReplaceNodeResults(
2767827675
return;
2767927676
}
2768027677
case Intrinsic::experimental_vector_match:
27681-
case Intrinsic::experimental_loop_dependence_raw_mask:
27682-
case Intrinsic::experimental_loop_dependence_war_mask: {
27678+
case Intrinsic::loop_dependence_raw_mask:
27679+
case Intrinsic::loop_dependence_war_mask: {
2768327680
if (!VT.isFixedLengthVector() || VT.getVectorElementType() != MVT::i1)
2768427681
return;
2768527682

‎llvm/test/CodeGen/AArch64/alias_mask.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ define <16 x i1> @whilewr_8(ptr %a, ptr %b) {
5151
; CHECK-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b
5252
; CHECK-NOSVE-NEXT: ret
5353
entry:
54-
%0 = call <16 x i1> @llvm.experimental.loop.dependence.war.mask.v16i1(ptr %a, ptr %b, i64 1)
54+
%0 = call <16 x i1> @llvm.loop.dependence.war.mask.v16i1(ptr %a, ptr %b, i64 1)
5555
ret <16 x i1> %0
5656
}
5757

@@ -91,7 +91,7 @@ define <8 x i1> @whilewr_16(ptr %a, ptr %b) {
9191
; CHECK-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b
9292
; CHECK-NOSVE-NEXT: ret
9393
entry:
94-
%0 = call <8 x i1> @llvm.experimental.loop.dependence.war.mask.v8i1(ptr %a, ptr %b, i64 2)
94+
%0 = call <8 x i1> @llvm.loop.dependence.war.mask.v8i1(ptr %a, ptr %b, i64 2)
9595
ret <8 x i1> %0
9696
}
9797

@@ -125,7 +125,7 @@ define <4 x i1> @whilewr_32(ptr %a, ptr %b) {
125125
; CHECK-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b
126126
; CHECK-NOSVE-NEXT: ret
127127
entry:
128-
%0 = call <4 x i1> @llvm.experimental.loop.dependence.war.mask.v4i1(ptr %a, ptr %b, i64 4)
128+
%0 = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1(ptr %a, ptr %b, i64 4)
129129
ret <4 x i1> %0
130130
}
131131

@@ -155,7 +155,7 @@ define <2 x i1> @whilewr_64(ptr %a, ptr %b) {
155155
; CHECK-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b
156156
; CHECK-NOSVE-NEXT: ret
157157
entry:
158-
%0 = call <2 x i1> @llvm.experimental.loop.dependence.war.mask.v2i1(ptr %a, ptr %b, i64 8)
158+
%0 = call <2 x i1> @llvm.loop.dependence.war.mask.v2i1(ptr %a, ptr %b, i64 8)
159159
ret <2 x i1> %0
160160
}
161161

@@ -209,7 +209,7 @@ define <16 x i1> @whilerw_8(ptr %a, ptr %b) {
209209
; CHECK-NOSVE-NEXT: orr v0.16b, v0.16b, v1.16b
210210
; CHECK-NOSVE-NEXT: ret
211211
entry:
212-
%0 = call <16 x i1> @llvm.experimental.loop.dependence.raw.mask.v16i1(ptr %a, ptr %b, i64 1)
212+
%0 = call <16 x i1> @llvm.loop.dependence.raw.mask.v16i1(ptr %a, ptr %b, i64 1)
213213
ret <16 x i1> %0
214214
}
215215

@@ -250,7 +250,7 @@ define <8 x i1> @whilerw_16(ptr %a, ptr %b) {
250250
; CHECK-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b
251251
; CHECK-NOSVE-NEXT: ret
252252
entry:
253-
%0 = call <8 x i1> @llvm.experimental.loop.dependence.raw.mask.v8i1(ptr %a, ptr %b, i64 2)
253+
%0 = call <8 x i1> @llvm.loop.dependence.raw.mask.v8i1(ptr %a, ptr %b, i64 2)
254254
ret <8 x i1> %0
255255
}
256256

@@ -285,7 +285,7 @@ define <4 x i1> @whilerw_32(ptr %a, ptr %b) {
285285
; CHECK-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b
286286
; CHECK-NOSVE-NEXT: ret
287287
entry:
288-
%0 = call <4 x i1> @llvm.experimental.loop.dependence.raw.mask.v4i1(ptr %a, ptr %b, i64 4)
288+
%0 = call <4 x i1> @llvm.loop.dependence.raw.mask.v4i1(ptr %a, ptr %b, i64 4)
289289
ret <4 x i1> %0
290290
}
291291

@@ -316,6 +316,6 @@ define <2 x i1> @whilerw_64(ptr %a, ptr %b) {
316316
; CHECK-NOSVE-NEXT: orr v0.8b, v0.8b, v1.8b
317317
; CHECK-NOSVE-NEXT: ret
318318
entry:
319-
%0 = call <2 x i1> @llvm.experimental.loop.dependence.raw.mask.v2i1(ptr %a, ptr %b, i64 8)
319+
%0 = call <2 x i1> @llvm.loop.dependence.raw.mask.v2i1(ptr %a, ptr %b, i64 8)
320320
ret <2 x i1> %0
321321
}

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