Use MCRegUnitMaskIterator instead

Author: sdesmalen-arm

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

@@ -745,15 +745,6 @@ class TargetRegisterInfo : public MCRegisterInfo {
     return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
   }
 
-  /// Returns the number of allocatable sub registers for R, which is the
-  /// number of register units that are not artificial and part of an
-  /// allocatable register class. For a register like D0_D1, which consists of
-  /// D0 and D1, this function would return '2'. For an architecture where
-  /// D0=S0_S1 and D1=S2_S3, this would return '4' for S0, S1, S2, S3.
-  unsigned getNumAllocatableSubRegs(MCPhysReg R) const {
-    return getNumAllocatableSubRegsImpl(R);
-  }
-
   /// Debugging helper: dump register in human readable form to dbgs() stream.
   static void dumpReg(Register Reg, unsigned SubRegIndex = 0,
                       const TargetRegisterInfo *TRI = nullptr);
@@ -783,10 +774,6 @@ class TargetRegisterInfo : public MCRegisterInfo {
     llvm_unreachable("Target has no sub-registers");
   }
 
-  virtual unsigned getNumAllocatableSubRegsImpl(MCPhysReg) const {
-    llvm_unreachable("Target has no sub-registers");
-  }
-
   /// Return the register cost table index. This implementation is sufficient
   /// for most architectures and can be overriden by targets in case there are
   /// multiple cost values associated with each register.

llvm/lib/CodeGen/LiveIntervals.cpp

@@ -730,7 +730,16 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
     // Find the regunit intervals for the assigned register. They may overlap
     // the virtual register live range, cancelling any kills.
     RU.clear();
-    for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+    LaneBitmask ArtificialLanes = LaneBitmask::getNone();
+    for (MCRegUnitMaskIterator UI(PhysReg, TRI); UI.isValid(); ++UI) {
+      auto [Unit, Bitmask] = *UI;
+      // Record lane mask for all artificial RegUnits for this physreg.
+      for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
+        if (TRI->isArtificial(*Root)) {
+          ArtificialLanes |= Bitmask;
+          break;
+        }
+      }
       const LiveRange &RURange = getRegUnit(Unit);
       if (RURange.empty())
         continue;
@@ -770,9 +779,6 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
       if (MRI->subRegLivenessEnabled()) {
         // When reading a partial undefined value we must not add a kill flag.
         // The regalloc might have used the undef lane for something else.
-        // If the register consists of a single allocatable subreg, then
-        // we can assume the other (undef) lanes cannot be used.
-        //
         // Example:
         //     %1 = ...                  ; R32: %1
         //     %2:high16 = ...           ; R64: %2
@@ -783,9 +789,13 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
         // are actually never written by %2. After assignment the <kill>
         // flag at the read instruction is invalid.
         LaneBitmask DefinedLanesMask;
-        if (LI.hasSubRanges() && TRI->getNumAllocatableSubRegs(PhysReg) > 1) {
+        if (LI.hasSubRanges()) {
           // Compute a mask of lanes that are defined.
-          DefinedLanesMask = LaneBitmask::getNone();
+          // Artificial regunits are not independently allocatable so the
+          // register allocator cannot have used them to represent any other
+          // values. That's why we mark them as 'defined' here, as this
+          // otherwise prevents kill flags from being added.
+          DefinedLanesMask = ArtificialLanes;
           for (const LiveInterval::SubRange &SR : LI.subranges())
             for (const LiveRange::Segment &Segment : SR.segments) {
               if (Segment.start >= RI->end)

llvm/utils/TableGen/RegisterInfoEmitter.cpp

@@ -93,8 +93,6 @@ class RegisterInfoEmitter {
   void EmitRegUnitPressure(raw_ostream &OS, StringRef ClassName);
   void emitComposeSubRegIndices(raw_ostream &OS, StringRef ClassName);
   void emitComposeSubRegIndexLaneMask(raw_ostream &OS, StringRef ClassName);
-  void emitNumAllocatableSubRegs(raw_ostream &OS, StringRef ClassName,
-                                 llvm::BitVector &InAllocClass);
 };
 
 } // end anonymous namespace
@@ -679,31 +677,6 @@ static bool combine(const CodeGenSubRegIndex *Idx,
   return true;
 }
 
-void RegisterInfoEmitter::emitNumAllocatableSubRegs(
-    raw_ostream &OS, StringRef ClassName, llvm::BitVector &InAllocClass) {
-  OS << "unsigned " << ClassName
-     << "::getNumAllocatableSubRegsImpl(MCPhysReg R) const {\n";
-  OS << "  static unsigned numAllocatableSubRegsMap[] = { \n";
-  OS << "    0, // NoRegister\n";
-  const auto &Regs = RegBank.getRegisters();
-  for (auto [I, R] : llvm::enumerate(Regs)) {
-    unsigned NumAllocatableSubRegs = 0;
-    for (unsigned U : R.getRegUnits()) {
-      for (const CodeGenRegister *UR : RegBank.getRegUnit(U).getRoots())
-        if (!UR->Artificial && InAllocClass[UR->EnumValue])
-          NumAllocatableSubRegs++;
-    }
-    OS << "    " << NumAllocatableSubRegs;
-    if (I < Regs.size() - 1)
-      OS << ",";
-    OS << " // " << R.getName() << "\n";
-  }
-  OS << "  };\n";
-  OS << "  assert(R <= " << Regs.size() << " && \"Unexpected physreg\");\n";
-  OS << "  return numAllocatableSubRegsMap[R];\n";
-  OS << "};\n";
-}
-
 void RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
                                                    StringRef ClassName) {
   const auto &SubRegIndices = RegBank.getSubRegIndices();
@@ -1149,9 +1122,7 @@ void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS) {
        << "  const TargetRegisterClass *getSubClassWithSubReg"
        << "(const TargetRegisterClass *, unsigned) const override;\n"
        << "  const TargetRegisterClass *getSubRegisterClass"
-       << "(const TargetRegisterClass *, unsigned) const override;\n"
-       << "  unsigned getNumAllocatableSubRegsImpl(MCPhysReg) const "
-          "override;\n";
+       << "(const TargetRegisterClass *, unsigned) const override;\n";
   }
   OS << "  const RegClassWeight &getRegClassWeight("
      << "const TargetRegisterClass *RC) const override;\n"
@@ -1512,7 +1483,6 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) {
   if (!SubRegIndices.empty()) {
     emitComposeSubRegIndices(OS, ClassName);
     emitComposeSubRegIndexLaneMask(OS, ClassName);
-    emitNumAllocatableSubRegs(OS, ClassName, InAllocClass);
   }
 
   if (!SubRegIndices.empty()) {