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[RISCV][GlobalISel] Zbkb support for G_ROTL and G_ROTR (#76599)
These instructions are legal in the presence of Zbkb extension.
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5 files changed

+67
-59
lines changed

5 files changed

+67
-59
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
101101
getActionDefinitionsBuilder({G_FSHL, G_FSHR}).lower();
102102

103103
auto &RotateActions = getActionDefinitionsBuilder({G_ROTL, G_ROTR});
104-
if (ST.hasStdExtZbb()) {
104+
if (ST.hasStdExtZbb() || ST.hasStdExtZbkb()) {
105105
RotateActions.legalFor({{s32, sXLen}, {sXLen, sXLen}});
106106
// Widen s32 rotate amount to s64 so SDAG patterns will match.
107107
if (ST.is64Bit())

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv32.mir

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
33
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4+
# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \
5+
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
46

57
---
68
name: rotl_i32

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv64.mir

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
33
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4+
# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=instruction-select \
5+
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
46

57
---
68
name: rotl_i32

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv32.mir

Lines changed: 19 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,9 @@
22
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
33
# RUN: | FileCheck %s --check-prefixes=CHECK,RV32I
44
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
5-
# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB
5+
# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB_OR_RV32ZBKB
6+
# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=legalizer %s -o - \
7+
# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB_OR_RV32ZBKB
68

79
---
810
name: rotl_i8
@@ -92,14 +94,14 @@ body: |
9294
; RV32I-NEXT: $x10 = COPY [[OR]](s32)
9395
; RV32I-NEXT: PseudoRET implicit $x10
9496
;
95-
; RV32ZBB-LABEL: name: rotl_i32
96-
; RV32ZBB: liveins: $x10, $x11
97-
; RV32ZBB-NEXT: {{ $}}
98-
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
99-
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
100-
; RV32ZBB-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[COPY1]](s32)
101-
; RV32ZBB-NEXT: $x10 = COPY [[ROTL]](s32)
102-
; RV32ZBB-NEXT: PseudoRET implicit $x10
97+
; RV32ZBB_OR_RV32ZBKB-LABEL: name: rotl_i32
98+
; RV32ZBB_OR_RV32ZBKB: liveins: $x10, $x11
99+
; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}
100+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
101+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
102+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[COPY1]](s32)
103+
; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[ROTL]](s32)
104+
; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10
103105
%0:_(s32) = COPY $x10
104106
%1:_(s32) = COPY $x11
105107
%2:_(s32) = G_ROTL %0, %1(s32)
@@ -260,14 +262,14 @@ body: |
260262
; RV32I-NEXT: $x10 = COPY [[OR]](s32)
261263
; RV32I-NEXT: PseudoRET implicit $x10
262264
;
263-
; RV32ZBB-LABEL: name: rotr_i32
264-
; RV32ZBB: liveins: $x10, $x11
265-
; RV32ZBB-NEXT: {{ $}}
266-
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
267-
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
268-
; RV32ZBB-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[COPY1]](s32)
269-
; RV32ZBB-NEXT: $x10 = COPY [[ROTR]](s32)
270-
; RV32ZBB-NEXT: PseudoRET implicit $x10
265+
; RV32ZBB_OR_RV32ZBKB-LABEL: name: rotr_i32
266+
; RV32ZBB_OR_RV32ZBKB: liveins: $x10, $x11
267+
; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}
268+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
269+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
270+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[COPY1]](s32)
271+
; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[ROTR]](s32)
272+
; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10
271273
%0:_(s32) = COPY $x10
272274
%1:_(s32) = COPY $x11
273275
%2:_(s32) = G_ROTR %0, %1(s32)

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir

Lines changed: 43 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,9 @@
22
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
33
# RUN: | FileCheck %s --check-prefixes=CHECK,RV64I
44
# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
5-
# RUN: | FileCheck %s --check-prefixes=CHECK,RV64ZBB
5+
# RUN: | FileCheck %s --check-prefixes=CHECK,RV64ZBB_OR_RV64ZBKB
6+
# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=legalizer %s -o - \
7+
# RUN: | FileCheck %s --check-prefixes=CHECK,RV64ZBB_OR_RV64ZBKB
68

79
---
810
name: rotl_i8
@@ -105,18 +107,18 @@ body: |
105107
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
106108
; RV64I-NEXT: PseudoRET implicit $x10
107109
;
108-
; RV64ZBB-LABEL: name: rotl_i32
109-
; RV64ZBB: liveins: $x10, $x11
110-
; RV64ZBB-NEXT: {{ $}}
111-
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
112-
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
113-
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
114-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
115-
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
116-
; RV64ZBB-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[TRUNC]], [[AND]](s64)
117-
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ROTL]](s32)
118-
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
119-
; RV64ZBB-NEXT: PseudoRET implicit $x10
110+
; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotl_i32
111+
; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11
112+
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
113+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
114+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
115+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
116+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
117+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
118+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[TRUNC]], [[AND]](s64)
119+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ROTL]](s32)
120+
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ANYEXT]](s64)
121+
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
120122
%2:_(s64) = COPY $x10
121123
%0:_(s32) = G_TRUNC %2(s64)
122124
%3:_(s64) = COPY $x11
@@ -149,14 +151,14 @@ body: |
149151
; RV64I-NEXT: $x10 = COPY [[OR]](s64)
150152
; RV64I-NEXT: PseudoRET implicit $x10
151153
;
152-
; RV64ZBB-LABEL: name: rotl_i64
153-
; RV64ZBB: liveins: $x10, $x11
154-
; RV64ZBB-NEXT: {{ $}}
155-
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
156-
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
157-
; RV64ZBB-NEXT: [[ROTL:%[0-9]+]]:_(s64) = G_ROTL [[COPY]], [[COPY1]](s64)
158-
; RV64ZBB-NEXT: $x10 = COPY [[ROTL]](s64)
159-
; RV64ZBB-NEXT: PseudoRET implicit $x10
154+
; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotl_i64
155+
; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11
156+
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
157+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
158+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
159+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTL:%[0-9]+]]:_(s64) = G_ROTL [[COPY]], [[COPY1]](s64)
160+
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ROTL]](s64)
161+
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
160162
%0:_(s64) = COPY $x10
161163
%1:_(s64) = COPY $x11
162164
%2:_(s64) = G_ROTL %0, %1(s64)
@@ -265,18 +267,18 @@ body: |
265267
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
266268
; RV64I-NEXT: PseudoRET implicit $x10
267269
;
268-
; RV64ZBB-LABEL: name: rotr_i32
269-
; RV64ZBB: liveins: $x10, $x11
270-
; RV64ZBB-NEXT: {{ $}}
271-
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
272-
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
273-
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
274-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
275-
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
276-
; RV64ZBB-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[TRUNC]], [[AND]](s64)
277-
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ROTR]](s32)
278-
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
279-
; RV64ZBB-NEXT: PseudoRET implicit $x10
270+
; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotr_i32
271+
; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11
272+
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
273+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
274+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
275+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
276+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
277+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
278+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[TRUNC]], [[AND]](s64)
279+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ROTR]](s32)
280+
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ANYEXT]](s64)
281+
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
280282
%2:_(s64) = COPY $x10
281283
%0:_(s32) = G_TRUNC %2(s64)
282284
%3:_(s64) = COPY $x11
@@ -309,14 +311,14 @@ body: |
309311
; RV64I-NEXT: $x10 = COPY [[OR]](s64)
310312
; RV64I-NEXT: PseudoRET implicit $x10
311313
;
312-
; RV64ZBB-LABEL: name: rotr_i64
313-
; RV64ZBB: liveins: $x10, $x11
314-
; RV64ZBB-NEXT: {{ $}}
315-
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
316-
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
317-
; RV64ZBB-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[COPY]], [[COPY1]](s64)
318-
; RV64ZBB-NEXT: $x10 = COPY [[ROTR]](s64)
319-
; RV64ZBB-NEXT: PseudoRET implicit $x10
314+
; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotr_i64
315+
; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11
316+
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
317+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
318+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
319+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[COPY]], [[COPY1]](s64)
320+
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ROTR]](s64)
321+
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
320322
%0:_(s64) = COPY $x10
321323
%1:_(s64) = COPY $x11
322324
%2:_(s64) = G_ROTR %0, %1(s64)

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