Exclude more uses of SHL that might be combined

Author: c-rhodes

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -26386,9 +26386,11 @@ static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG) {
   if (!C1 || !C2)
     return SDValue();
 
-  // Might be folded into shifted add/sub, do not lower.
-  if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ADD ||
-                         N->use_begin()->getOpcode() == ISD::SUB))
+  // Might be folded into shifted op, do not lower.
+  unsigned UseOpc = N->use_begin()->getOpcode();
+  if (N->hasOneUse() &&
+      (UseOpc == ISD::ADD || UseOpc == ISD::SUB || UseOpc == ISD::SETCC ||
+       UseOpc == AArch64ISD::ADDS || UseOpc == AArch64ISD::SUBS))
     return SDValue();
 
   SDLoc DL(N);

llvm/test/CodeGen/AArch64/swap-compare-operands.ll

@@ -133,9 +133,8 @@ entry:
 
 define i1 @testSwapCmpWithShiftedZeroExtend16_64(i16 %a, i64 %b) {
 ; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend16_64
-; CHECK:      ubfiz  x8, x0, #2, #16
-; CHECK:      cmp    x8, x1
-; CHECK-NEXT: cset   w0, hi
+; CHECK:      cmp    x1, w0, uxth #2
+; CHECK-NEXT: cset   w0, lo
 entry:
   %a64 = zext i16 %a to i64
   %shl.0 = shl i64 %a64, 2
@@ -145,9 +144,8 @@ entry:
 
 define i1 @testSwapCmpWithShiftedZeroExtend8_64(i8 %a, i64 %b) {
 ; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend8_64
-; CHECK:      ubfiz  x8, x0, #4, #8
-; CHECK:      cmp    x8, x1
-; CHECK-NEXT: cset    w0, hi
+; CHECK:      cmp    x1, w0, uxtb #4
+; CHECK-NEXT: cset    w0, lo
 entry:
   %a64 = zext i8 %a to i64
   %shl.2 = shl i64 %a64, 4
@@ -157,9 +155,8 @@ entry:
 
 define i1 @testSwapCmpWithShiftedZeroExtend16_32(i16 %a, i32 %b) {
 ; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend16_32
-; CHECK:      ubfiz  w8, w0, #3, #16
-; CHECK:      cmp    w8, w1
-; CHECK-NEXT: cset    w0, hi
+; CHECK:      cmp    w1, w0, uxth #3
+; CHECK-NEXT: cset    w0, lo
 entry:
   %a32 = zext i16 %a to i32
   %shl = shl i32 %a32, 3
@@ -169,9 +166,8 @@ entry:
 
 define i1 @testSwapCmpWithShiftedZeroExtend8_32(i8 %a, i32 %b) {
 ; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend8_32
-; CHECK:      ubfiz  w8, w0, #4, #8
-; CHECK:      cmp    w8, w1
-; CHECK-NEXT: cset    w0, hi
+; CHECK:      cmp    w1, w0, uxtb #4
+; CHECK-NEXT: cset    w0, lo
 entry:
   %a32 = zext i8 %a to i32
   %shl = shl i32 %a32, 4
@@ -181,9 +177,9 @@ entry:
 
 define i1 @testSwapCmpWithTooLargeShiftedZeroExtend8_32(i8 %a, i32 %b) {
 ; CHECK-LABEL: testSwapCmpWithTooLargeShiftedZeroExtend8_32
-; CHECK:      ubfiz  w8, w0, #5, #8
-; CHECK:      cmp    w8, w1
-; CHECK-NEXT: cset   w0, hi
+; CHECK:      and    [[REG:w[0-9]+]], w0, #0xff
+; CHECK:      cmp    w1, [[REG]], lsl #5
+; CHECK-NEXT: cset   w0, lo
 entry:
   %a32 = zext i8 %a to i32
   %shl = shl i32 %a32, 5
@@ -521,44 +517,40 @@ t1:
   %shl1 = shl i64 %conv1, 4
   %na1 = sub i64 0, %shl1
   %cmp1 = icmp ne i64 %na1, %b64
-; CHECK: ubfiz  x8, x1, #4, #16
-; CHECK: cmn    x3, x8
+; CHECK: cmn    x3, w1, uxth #4
   br i1 %cmp1, label %t2, label %end
 
 t2:
   %conv2 = zext i8 %a8 to i64
   %shl2 = shl i64 %conv2, 3
   %na2 = sub i64 0, %shl2
   %cmp2 = icmp ne i64 %na2, %b64
-; CHECK: ubfiz  x8, x2, #3, #8
-; CHECK: cmn    x3, x8
+; CHECK: cmn    x3, w2, uxtb #3
   br i1 %cmp2, label %t3, label %end
 
 t3:
   %conv3 = zext i16 %a16 to i32
   %shl3 = shl i32 %conv3, 2
   %na3 = sub i32 0, %shl3
   %cmp3 = icmp ne i32 %na3, %b32
-; CHECK: ubfiz  w8, w1, #2, #16
-; CHECK: cmn    w4, w8
+; CHECK: cmn    w4, w1, uxth #2
   br i1 %cmp3, label %t4, label %end
 
 t4:
   %conv4 = zext i8 %a8 to i32
   %shl4 = shl i32 %conv4, 1
   %na4 = sub i32 0, %shl4
   %cmp4 = icmp ne i32 %na4, %b32
-; CHECK: ubfiz  w8, w2, #1, #8
-; CHECK: cmn    w4, w8
+; CHECK: cmn    w4, w2, uxtb #1
   br i1 %cmp4, label %t5, label %end
 
 t5:
   %conv5 = zext i8 %a8 to i32
   %shl5 = shl i32 %conv5, 5
   %na5 = sub i32 0, %shl5
   %cmp5 = icmp ne i32 %na5, %b32
-; CHECK: ubfiz  w8, w2, #5, #8
-; CHECK: cmn    w4, w8
+; CHECK: and    [[REG:w[0-9]+]], w2, #0xff
+; CHECK: cmn    w4, [[REG]], lsl #5
   br i1 %cmp5, label %t6, label %end
 
 t6: