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[RISCV] Support vrgather and vcompress for zvfhmin and zvfbfmin (#101633)
Support these in both C intrinsics and CodeGen, they can work with other intrinsics in `zvfhmin` or `zvfbfmin`. This resolve: riscv-non-isa/rvv-intrinsic-doc#350
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12 files changed

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‎clang/include/clang/Basic/riscv_vector.td

Lines changed: 21 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2262,10 +2262,22 @@ defm vfslide1down : RVVFloatingBinVFBuiltinSet;
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// 16.4. Vector Register Gather Instructions
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// signed and floating type
2265-
defm vrgather : RVVOutBuiltinSet<"vrgather_vv", "csilxfd",
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defm vrgather : RVVOutBuiltinSet<"vrgather_vv", "csilfd",
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[["vv", "v", "vvUv"]]>;
2267-
defm vrgather : RVVOutBuiltinSet<"vrgather_vx", "csilxfd",
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defm vrgather : RVVOutBuiltinSet<"vrgather_vx", "csilfd",
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[["vx", "v", "vvz"]]>;
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let RequiredFeatures = ["Zvfhmin"] in {
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defm vrgather : RVVOutBuiltinSet<"vrgather_vv", "x",
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[["vv", "v", "vvUv"]]>;
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defm vrgather : RVVOutBuiltinSet<"vrgather_vx", "x",
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[["vx", "v", "vvz"]]>;
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}
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let RequiredFeatures = ["Zvfbfmin"] in {
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defm vrgather : RVVOutBuiltinSet<"vrgather_vv", "y",
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[["vv", "v", "vvUv"]]>;
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defm vrgather : RVVOutBuiltinSet<"vrgather_vx", "y",
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[["vx", "v", "vvz"]]>;
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}
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defm vrgatherei16 : RVVOutBuiltinSet<"vrgatherei16_vv", "csilxfd",
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[["vv", "v", "vv(Log2EEW:4)Uv"]]>;
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// unsigned type
@@ -2288,8 +2300,14 @@ let HasMasked = false,
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IntrinsicTypes = {ResultType, Ops.back()->getType()};
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}] in {
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// signed and floating type
2291-
defm vcompress : RVVOutBuiltinSet<"vcompress", "csilxfd",
2303+
defm vcompress : RVVOutBuiltinSet<"vcompress", "csilfd",
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[["vm", "v", "vvm"]]>;
2305+
let RequiredFeatures = ["Zvfhmin"] in
2306+
defm vcompress : RVVOutBuiltinSet<"vcompress", "x",
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[["vm", "v", "vvm"]]>;
2308+
let RequiredFeatures = ["Zvfbfmin"] in
2309+
defm vcompress : RVVOutBuiltinSet<"vcompress", "y",
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[["vm", "v", "vvm"]]>;
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// unsigned type
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defm vcompress : RVVOutBuiltinSet<"vcompress", "csil",
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[["vm", "Uv", "UvUvm"]]>;

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c

Lines changed: 61 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
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// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone \
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// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
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// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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@@ -597,3 +597,63 @@ vuint64m8_t test_vcompress_vm_u64m8(vuint64m8_t src, vbool8_t mask, size_t vl) {
597597
return __riscv_vcompress_vm_u64m8(src, mask, vl);
598598
}
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600+
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4
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// CHECK-RV64-SAME: (<vscale x 1 x bfloat> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
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//
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vbfloat16mf4_t test_vcompress_vm_bf16mf4(vbfloat16mf4_t src, vbool64_t mask, size_t vl) {
607+
return __riscv_vcompress_vm_bf16mf4(src, mask, vl);
608+
}
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610+
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2
611+
// CHECK-RV64-SAME: (<vscale x 2 x bfloat> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
613+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
614+
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
615+
//
616+
vbfloat16mf2_t test_vcompress_vm_bf16mf2(vbfloat16mf2_t src, vbool32_t mask, size_t vl) {
617+
return __riscv_vcompress_vm_bf16mf2(src, mask, vl);
618+
}
619+
620+
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1
621+
// CHECK-RV64-SAME: (<vscale x 4 x bfloat> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
622+
// CHECK-RV64-NEXT: entry:
623+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
624+
// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
625+
//
626+
vbfloat16m1_t test_vcompress_vm_bf16m1(vbfloat16m1_t src, vbool16_t mask, size_t vl) {
627+
return __riscv_vcompress_vm_bf16m1(src, mask, vl);
628+
}
629+
630+
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2
631+
// CHECK-RV64-SAME: (<vscale x 8 x bfloat> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
632+
// CHECK-RV64-NEXT: entry:
633+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
634+
// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
635+
//
636+
vbfloat16m2_t test_vcompress_vm_bf16m2(vbfloat16m2_t src, vbool8_t mask, size_t vl) {
637+
return __riscv_vcompress_vm_bf16m2(src, mask, vl);
638+
}
639+
640+
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4
641+
// CHECK-RV64-SAME: (<vscale x 16 x bfloat> [[SRC:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
642+
// CHECK-RV64-NEXT: entry:
643+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
644+
// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
645+
//
646+
vbfloat16m4_t test_vcompress_vm_bf16m4(vbfloat16m4_t src, vbool4_t mask, size_t vl) {
647+
return __riscv_vcompress_vm_bf16m4(src, mask, vl);
648+
}
649+
650+
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8
651+
// CHECK-RV64-SAME: (<vscale x 32 x bfloat> [[SRC:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
652+
// CHECK-RV64-NEXT: entry:
653+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
654+
// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
655+
//
656+
vbfloat16m8_t test_vcompress_vm_bf16m8(vbfloat16m8_t src, vbool2_t mask, size_t vl) {
657+
return __riscv_vcompress_vm_bf16m8(src, mask, vl);
658+
}
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