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[GISel][RISCV] Add irtranslator/legalizer/selector support for G_FREEZE. (#92744)
This patch adds support for G_FREEZE on riscv. It will be selected into a copy instruction. The ll test is copied from the AArch64 patch: 665da59.
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6 files changed

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6 files changed

+364
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lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -558,6 +558,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
558558
case TargetOpcode::G_PTRTOINT:
559559
case TargetOpcode::G_INTTOPTR:
560560
case TargetOpcode::G_TRUNC:
561+
case TargetOpcode::G_FREEZE:
561562
return selectCopy(MI, MRI);
562563
case TargetOpcode::G_CONSTANT: {
563564
Register DstReg = MI.getOperand(0).getReg();

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -227,7 +227,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
227227
ConstantActions.widenScalarToNextPow2(0).clampScalar(0, s32, sXLen);
228228

229229
// TODO: transform illegal vector types into legal vector type
230-
getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_CONSTANT_FOLD_BARRIER})
230+
getActionDefinitionsBuilder(
231+
{G_IMPLICIT_DEF, G_CONSTANT_FOLD_BARRIER, G_FREEZE})
231232
.legalFor({s32, sXLen, p0})
232233
.legalIf(typeIsLegalBoolVec(0, BoolVecTys, ST))
233234
.legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21443,7 +21443,8 @@ bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
2144321443
if (Op == Instruction::Add || Op == Instruction::Sub ||
2144421444
Op == Instruction::And || Op == Instruction::Or ||
2144521445
Op == Instruction::Xor || Op == Instruction::InsertElement ||
21446-
Op == Instruction::ShuffleVector || Op == Instruction::Load)
21446+
Op == Instruction::ShuffleVector || Op == Instruction::Load ||
21447+
Op == Instruction::Freeze)
2144721448
return false;
2144821449

2144921450
if (Inst.getType()->isScalableTy())

‎llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll

Lines changed: 201 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,201 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfh,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV32
3+
; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV64
4+
5+
define i32 @freeze_int(i32 %x) {
6+
; RV32-LABEL: freeze_int:
7+
; RV32: # %bb.0:
8+
; RV32-NEXT: mul a0, a0, a0
9+
; RV32-NEXT: ret
10+
;
11+
; RV64-LABEL: freeze_int:
12+
; RV64: # %bb.0:
13+
; RV64-NEXT: mulw a0, a0, a0
14+
; RV64-NEXT: ret
15+
%y1 = freeze i32 %x
16+
%t1 = mul i32 %y1, %y1
17+
ret i32 %t1
18+
}
19+
20+
define i5 @freeze_int2(i5 %x) {
21+
; RV32-LABEL: freeze_int2:
22+
; RV32: # %bb.0:
23+
; RV32-NEXT: mul a0, a0, a0
24+
; RV32-NEXT: ret
25+
;
26+
; RV64-LABEL: freeze_int2:
27+
; RV64: # %bb.0:
28+
; RV64-NEXT: mulw a0, a0, a0
29+
; RV64-NEXT: ret
30+
%y1 = freeze i5 %x
31+
%t1 = mul i5 %y1, %y1
32+
ret i5 %t1
33+
}
34+
35+
define float @freeze_float(float %x) {
36+
; CHECK-LABEL: freeze_float:
37+
; CHECK: # %bb.0:
38+
; CHECK-NEXT: fadd.s fa0, fa0, fa0
39+
; CHECK-NEXT: ret
40+
%y1 = freeze float %x
41+
%t1 = fadd float %y1, %y1
42+
ret float %t1
43+
}
44+
45+
define double @freeze_double(double %x) nounwind {
46+
; RV32-LABEL: freeze_double:
47+
; RV32: # %bb.0:
48+
; RV32-NEXT: addi sp, sp, -16
49+
; RV32-NEXT: fsd fa0, 8(sp)
50+
; RV32-NEXT: lw a0, 8(sp)
51+
; RV32-NEXT: lw a1, 12(sp)
52+
; RV32-NEXT: sw a0, 8(sp)
53+
; RV32-NEXT: sw a1, 12(sp)
54+
; RV32-NEXT: fld fa5, 8(sp)
55+
; RV32-NEXT: fadd.d fa0, fa5, fa5
56+
; RV32-NEXT: addi sp, sp, 16
57+
; RV32-NEXT: ret
58+
;
59+
; RV64-LABEL: freeze_double:
60+
; RV64: # %bb.0:
61+
; RV64-NEXT: fadd.d fa0, fa0, fa0
62+
; RV64-NEXT: ret
63+
%y1 = freeze double %x
64+
%t1 = fadd double %y1, %y1
65+
ret double %t1
66+
}
67+
68+
define void @freeze_half(ptr %p) {
69+
; CHECK-LABEL: freeze_half:
70+
; CHECK: # %bb.0:
71+
; CHECK-NEXT: lh a1, 0(a0)
72+
; CHECK-NEXT: sh a1, 0(a0)
73+
; CHECK-NEXT: ret
74+
%x = load half, ptr %p
75+
%y1 = freeze half %x
76+
store half %y1, ptr %p
77+
ret void
78+
}
79+
80+
define <vscale x 2 x i32> @freeze_ivec(<vscale x 2 x i32> %x) {
81+
; CHECK-LABEL: freeze_ivec:
82+
; CHECK: # %bb.0:
83+
; CHECK-NEXT: ret
84+
%y = freeze <vscale x 2 x i32> %x
85+
ret <vscale x 2 x i32> %y
86+
}
87+
88+
define <vscale x 2 x float> @freeze_fvec(<vscale x 2 x float> %x) {
89+
; CHECK-LABEL: freeze_fvec:
90+
; CHECK: # %bb.0:
91+
; CHECK-NEXT: ret
92+
%y = freeze <vscale x 2 x float> %x
93+
ret <vscale x 2 x float> %y
94+
}
95+
96+
define ptr @freeze_ptr(ptr %x) {
97+
; CHECK-LABEL: freeze_ptr:
98+
; CHECK: # %bb.0:
99+
; CHECK-NEXT: addi a0, a0, 4
100+
; CHECK-NEXT: ret
101+
%y1 = freeze ptr %x
102+
%t1 = getelementptr i8, ptr %y1, i64 4
103+
ret ptr %t1
104+
}
105+
106+
%struct.T = type { i32, i32 }
107+
108+
define i32 @freeze_struct(ptr %p) {
109+
; RV32-LABEL: freeze_struct:
110+
; RV32: # %bb.0:
111+
; RV32-NEXT: lw a1, 0(a0)
112+
; RV32-NEXT: lw a0, 4(a0)
113+
; RV32-NEXT: add a0, a1, a0
114+
; RV32-NEXT: ret
115+
;
116+
; RV64-LABEL: freeze_struct:
117+
; RV64: # %bb.0:
118+
; RV64-NEXT: lw a1, 0(a0)
119+
; RV64-NEXT: lw a0, 4(a0)
120+
; RV64-NEXT: addw a0, a1, a0
121+
; RV64-NEXT: ret
122+
%s = load %struct.T, ptr %p
123+
%y1 = freeze %struct.T %s
124+
%v1 = extractvalue %struct.T %y1, 0
125+
%v2 = extractvalue %struct.T %y1, 1
126+
%t1 = add i32 %v1, %v2
127+
ret i32 %t1
128+
}
129+
130+
define i32 @freeze_anonstruct(ptr %p) {
131+
; RV32-LABEL: freeze_anonstruct:
132+
; RV32: # %bb.0:
133+
; RV32-NEXT: lw a1, 0(a0)
134+
; RV32-NEXT: lw a0, 4(a0)
135+
; RV32-NEXT: add a0, a1, a0
136+
; RV32-NEXT: ret
137+
;
138+
; RV64-LABEL: freeze_anonstruct:
139+
; RV64: # %bb.0:
140+
; RV64-NEXT: lw a1, 0(a0)
141+
; RV64-NEXT: lw a0, 4(a0)
142+
; RV64-NEXT: addw a0, a1, a0
143+
; RV64-NEXT: ret
144+
%s = load {i32, i32}, ptr %p
145+
%y1 = freeze {i32, i32} %s
146+
%v1 = extractvalue {i32, i32} %y1, 0
147+
%v2 = extractvalue {i32, i32} %y1, 1
148+
%t1 = add i32 %v1, %v2
149+
ret i32 %t1
150+
}
151+
152+
define i32 @freeze_anonstruct2(ptr %p) {
153+
; RV32-LABEL: freeze_anonstruct2:
154+
; RV32: # %bb.0:
155+
; RV32-NEXT: lh a1, 4(a0)
156+
; RV32-NEXT: lw a0, 0(a0)
157+
; RV32-NEXT: lui a2, 16
158+
; RV32-NEXT: addi a2, a2, -1
159+
; RV32-NEXT: and a1, a1, a2
160+
; RV32-NEXT: add a0, a0, a1
161+
; RV32-NEXT: ret
162+
;
163+
; RV64-LABEL: freeze_anonstruct2:
164+
; RV64: # %bb.0:
165+
; RV64-NEXT: lh a1, 4(a0)
166+
; RV64-NEXT: lw a0, 0(a0)
167+
; RV64-NEXT: lui a2, 16
168+
; RV64-NEXT: addi a2, a2, -1
169+
; RV64-NEXT: and a1, a1, a2
170+
; RV64-NEXT: addw a0, a0, a1
171+
; RV64-NEXT: ret
172+
%s = load {i32, i16}, ptr %p
173+
%y1 = freeze {i32, i16} %s
174+
%v1 = extractvalue {i32, i16} %y1, 0
175+
%v2 = extractvalue {i32, i16} %y1, 1
176+
%z2 = zext i16 %v2 to i32
177+
%t1 = add i32 %v1, %z2
178+
ret i32 %t1
179+
}
180+
181+
define i32 @freeze_array(ptr %p) nounwind {
182+
; RV32-LABEL: freeze_array:
183+
; RV32: # %bb.0:
184+
; RV32-NEXT: lw a1, 0(a0)
185+
; RV32-NEXT: lw a0, 4(a0)
186+
; RV32-NEXT: add a0, a1, a0
187+
; RV32-NEXT: ret
188+
;
189+
; RV64-LABEL: freeze_array:
190+
; RV64: # %bb.0:
191+
; RV64-NEXT: lw a1, 0(a0)
192+
; RV64-NEXT: lw a0, 4(a0)
193+
; RV64-NEXT: addw a0, a1, a0
194+
; RV64-NEXT: ret
195+
%s = load [2 x i32], ptr %p
196+
%y1 = freeze [2 x i32] %s
197+
%v1 = extractvalue [2 x i32] %y1, 0
198+
%v2 = extractvalue [2 x i32] %y1, 1
199+
%t1 = add i32 %v1, %v2
200+
ret i32 %t1
201+
}

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv32.mir

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,62 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2+
# RUN: llc -mtriple=riscv32 -mattr=+f,+v -run-pass=legalizer %s -o - | FileCheck %s
3+
---
4+
name: freeze_i32
5+
body: |
6+
bb.0.entry:
7+
; CHECK-LABEL: name: freeze_i32
8+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
9+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
10+
; CHECK-NEXT: $x10 = COPY [[FREEZE]](s32)
11+
; CHECK-NEXT: PseudoRET implicit $x10
12+
%1:_(s32) = COPY $x10
13+
%2:_(s32) = G_FREEZE %1
14+
$x10 = COPY %2(s32)
15+
PseudoRET implicit $x10
16+
17+
...
18+
---
19+
name: freeze_f32
20+
body: |
21+
bb.0.entry:
22+
; CHECK-LABEL: name: freeze_f32
23+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
24+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
25+
; CHECK-NEXT: $f10_f = COPY [[FREEZE]](s32)
26+
; CHECK-NEXT: PseudoRET implicit $f10_f
27+
%1:_(s32) = COPY $f10_f
28+
%2:_(s32) = G_FREEZE %1
29+
$f10_f = COPY %2(s32)
30+
PseudoRET implicit $f10_f
31+
32+
...
33+
---
34+
name: freeze_nxv2i1
35+
body: |
36+
bb.0.entry:
37+
; CHECK-LABEL: name: freeze_nxv2i1
38+
; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8
39+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s1>) = G_FREEZE [[COPY]]
40+
; CHECK-NEXT: $v8 = COPY [[FREEZE]](<vscale x 2 x s1>)
41+
; CHECK-NEXT: PseudoRET implicit $v8
42+
%1:_(<vscale x 2 x s1>) = COPY $v8
43+
%2:_(<vscale x 2 x s1>) = G_FREEZE %1
44+
$v8 = COPY %2(<vscale x 2 x s1>)
45+
PseudoRET implicit $v8
46+
47+
...
48+
---
49+
name: freeze_nxv2i32
50+
body: |
51+
bb.0.entry:
52+
; CHECK-LABEL: name: freeze_nxv2i32
53+
; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
54+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s32>) = G_FREEZE [[COPY]]
55+
; CHECK-NEXT: $v8 = COPY [[FREEZE]](<vscale x 2 x s32>)
56+
; CHECK-NEXT: PseudoRET implicit $v8
57+
%1:_(<vscale x 2 x s32>) = COPY $v8
58+
%2:_(<vscale x 2 x s32>) = G_FREEZE %1
59+
$v8 = COPY %2(<vscale x 2 x s32>)
60+
PseudoRET implicit $v8
61+
62+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-freeze-rv64.mir

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,96 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2+
# RUN: llc -mtriple=riscv64 -mattr=+f,+v -run-pass=legalizer %s -o - | FileCheck %s
3+
---
4+
name: freeze_i32
5+
body: |
6+
bb.0.entry:
7+
; CHECK-LABEL: name: freeze_i32
8+
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
9+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
10+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[TRUNC]]
11+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s32)
12+
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
13+
; CHECK-NEXT: PseudoRET implicit $x10
14+
%1:_(s64) = COPY $x10
15+
%2:_(s32) = G_TRUNC %1(s64)
16+
%3:_(s32) = G_FREEZE %2
17+
%4:_(s64) = G_ANYEXT %3(s32)
18+
$x10 = COPY %4(s64)
19+
PseudoRET implicit $x10
20+
21+
...
22+
---
23+
name: freeze_f32
24+
body: |
25+
bb.0.entry:
26+
; CHECK-LABEL: name: freeze_f32
27+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
28+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
29+
; CHECK-NEXT: $f10_f = COPY [[FREEZE]](s32)
30+
; CHECK-NEXT: PseudoRET implicit $f10_f
31+
%1:_(s32) = COPY $f10_f
32+
%2:_(s32) = G_FREEZE %1
33+
$f10_f = COPY %2(s32)
34+
PseudoRET implicit $f10_f
35+
36+
...
37+
---
38+
name: freeze_i64
39+
body: |
40+
bb.0.entry:
41+
; CHECK-LABEL: name: freeze_i64
42+
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
43+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[COPY]]
44+
; CHECK-NEXT: $x10 = COPY [[FREEZE]](s64)
45+
; CHECK-NEXT: PseudoRET implicit $x10
46+
%1:_(s64) = COPY $x10
47+
%2:_(s64) = G_FREEZE %1
48+
$x10 = COPY %2(s64)
49+
PseudoRET implicit $x10
50+
51+
...
52+
---
53+
name: freeze_nxv2i1
54+
body: |
55+
bb.0.entry:
56+
; CHECK-LABEL: name: freeze_nxv2i1
57+
; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8
58+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s1>) = G_FREEZE [[COPY]]
59+
; CHECK-NEXT: $v8 = COPY [[FREEZE]](<vscale x 2 x s1>)
60+
; CHECK-NEXT: PseudoRET implicit $v8
61+
%1:_(<vscale x 2 x s1>) = COPY $v8
62+
%2:_(<vscale x 2 x s1>) = G_FREEZE %1
63+
$v8 = COPY %2(<vscale x 2 x s1>)
64+
PseudoRET implicit $v8
65+
66+
...
67+
---
68+
name: freeze_nxv2i32
69+
body: |
70+
bb.0.entry:
71+
; CHECK-LABEL: name: freeze_nxv2i32
72+
; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
73+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s32>) = G_FREEZE [[COPY]]
74+
; CHECK-NEXT: $v8 = COPY [[FREEZE]](<vscale x 2 x s32>)
75+
; CHECK-NEXT: PseudoRET implicit $v8
76+
%1:_(<vscale x 2 x s32>) = COPY $v8
77+
%2:_(<vscale x 2 x s32>) = G_FREEZE %1
78+
$v8 = COPY %2(<vscale x 2 x s32>)
79+
PseudoRET implicit $v8
80+
81+
...
82+
---
83+
name: freeze_nxv2i64
84+
body: |
85+
bb.0.entry:
86+
; CHECK-LABEL: name: freeze_nxv2i64
87+
; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8
88+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<vscale x 2 x s64>) = G_FREEZE [[COPY]]
89+
; CHECK-NEXT: $v8m2 = COPY [[FREEZE]](<vscale x 2 x s64>)
90+
; CHECK-NEXT: PseudoRET implicit $v8m2
91+
%1:_(<vscale x 2 x s64>) = COPY $v8
92+
%2:_(<vscale x 2 x s64>) = G_FREEZE %1
93+
$v8m2 = COPY %2(<vscale x 2 x s64>)
94+
PseudoRET implicit $v8m2
95+
96+
...

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