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[Sparc] Remove custom lowering for SMULO / UMULO (#100858)
The underlying issue was fixed by 7c4fe0e. The lowering is tested by [us]mulo-128-legalisation-lowering.ll and there are no changes.
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2 files changed

+102
-113
lines changed

2 files changed

+102
-113
lines changed

‎llvm/lib/Target/Sparc/SparcISelLowering.cpp

Lines changed: 0 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -1855,9 +1855,6 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
18551855
setOperationAction(ISD::MULHU, MVT::i64, Expand);
18561856
setOperationAction(ISD::MULHS, MVT::i64, Expand);
18571857

1858-
setOperationAction(ISD::UMULO, MVT::i64, Custom);
1859-
setOperationAction(ISD::SMULO, MVT::i64, Custom);
1860-
18611858
setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
18621859
setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
18631860
setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
@@ -3154,61 +3151,6 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
31543151
return DAG.getMergeValues(Ops, dl);
31553152
}
31563153

3157-
// Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
3158-
// in LegalizeDAG.cpp except the order of arguments to the library function.
3159-
static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
3160-
const SparcTargetLowering &TLI)
3161-
{
3162-
unsigned opcode = Op.getOpcode();
3163-
assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
3164-
3165-
bool isSigned = (opcode == ISD::SMULO);
3166-
EVT VT = MVT::i64;
3167-
EVT WideVT = MVT::i128;
3168-
SDLoc dl(Op);
3169-
SDValue LHS = Op.getOperand(0);
3170-
3171-
if (LHS.getValueType() != VT)
3172-
return Op;
3173-
3174-
SDValue ShiftAmt = DAG.getConstant(63, dl, VT);
3175-
3176-
SDValue RHS = Op.getOperand(1);
3177-
SDValue HiLHS, HiRHS;
3178-
if (isSigned) {
3179-
HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
3180-
HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
3181-
} else {
3182-
HiLHS = DAG.getConstant(0, dl, VT);
3183-
HiRHS = DAG.getConstant(0, dl, MVT::i64);
3184-
}
3185-
3186-
SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
3187-
3188-
TargetLowering::MakeLibCallOptions CallOptions;
3189-
CallOptions.setSExt(isSigned);
3190-
SDValue MulResult = TLI.makeLibCall(DAG,
3191-
RTLIB::MUL_I128, WideVT,
3192-
Args, CallOptions, dl).first;
3193-
SDValue BottomHalf, TopHalf;
3194-
std::tie(BottomHalf, TopHalf) = DAG.SplitScalar(MulResult, dl, VT, VT);
3195-
if (isSigned) {
3196-
SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
3197-
TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
3198-
} else {
3199-
TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT),
3200-
ISD::SETNE);
3201-
}
3202-
// MulResult is a node with an illegal type. Because such things are not
3203-
// generally permitted during this phase of legalization, ensure that
3204-
// nothing is left using the node. The above EXTRACT_ELEMENT nodes should have
3205-
// been folded.
3206-
assert(MulResult->use_empty() && "Illegally typed node still in use!");
3207-
3208-
SDValue Ops[2] = { BottomHalf, TopHalf } ;
3209-
return DAG.getMergeValues(Ops, dl);
3210-
}
3211-
32123154
static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
32133155
if (isStrongerThanMonotonic(cast<AtomicSDNode>(Op)->getSuccessOrdering())) {
32143156
// Expand with a fence.
@@ -3287,8 +3229,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
32873229
case ISD::ADDE:
32883230
case ISD::SUBC:
32893231
case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
3290-
case ISD::UMULO:
3291-
case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
32923232
case ISD::ATOMIC_LOAD:
32933233
case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
32943234
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);

‎llvm/test/CodeGen/SPARC/64cond.ll

Lines changed: 102 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,19 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
12
; RUN: llc < %s -mtriple=sparc64-pc-openbsd -disable-sparc-leaf-proc | FileCheck %s
23
; Testing 64-bit conditionals. The sparc64 triple is an alias for sparcv9.
34

4-
; CHECK: cmpri
5-
; CHECK: cmp %i1, 1
6-
; CHECK: be %xcc,
7-
define void @cmpri(ptr %p, i64 %x) {
5+
define void @cmpri(ptr %p, i64 %x) nounwind {
6+
; CHECK-LABEL: cmpri:
7+
; CHECK: ! %bb.0: ! %entry
8+
; CHECK-NEXT: save %sp, -128, %sp
9+
; CHECK-NEXT: cmp %i1, 1
10+
; CHECK-NEXT: be %xcc, .LBB0_2
11+
; CHECK-NEXT: nop
12+
; CHECK-NEXT: ! %bb.1: ! %if.then
13+
; CHECK-NEXT: stx %i1, [%i0]
14+
; CHECK-NEXT: .LBB0_2: ! %if.end
15+
; CHECK-NEXT: ret
16+
; CHECK-NEXT: restore
817
entry:
918
%tobool = icmp eq i64 %x, 1
1019
br i1 %tobool, label %if.end, label %if.then
@@ -17,10 +26,18 @@ if.end:
1726
ret void
1827
}
1928

20-
; CHECK: cmprr
21-
; CHECK: cmp %i1, %i2
22-
; CHECK: bgu %xcc,
23-
define void @cmprr(ptr %p, i64 %x, i64 %y) {
29+
define void @cmprr(ptr %p, i64 %x, i64 %y) nounwind {
30+
; CHECK-LABEL: cmprr:
31+
; CHECK: ! %bb.0: ! %entry
32+
; CHECK-NEXT: save %sp, -128, %sp
33+
; CHECK-NEXT: cmp %i1, %i2
34+
; CHECK-NEXT: bgu %xcc, .LBB1_2
35+
; CHECK-NEXT: nop
36+
; CHECK-NEXT: ! %bb.1: ! %if.then
37+
; CHECK-NEXT: stx %i1, [%i0]
38+
; CHECK-NEXT: .LBB1_2: ! %if.end
39+
; CHECK-NEXT: ret
40+
; CHECK-NEXT: restore
2441
entry:
2542
%tobool = icmp ugt i64 %x, %y
2643
br i1 %tobool, label %if.end, label %if.then
@@ -33,94 +50,126 @@ if.end:
3350
ret void
3451
}
3552

36-
; CHECK: selecti32_xcc
37-
; CHECK: cmp %i0, %i1
38-
; CHECK: movg %xcc, %i2, %i3
39-
; CHECK: restore %g0, %i3, %o0
40-
define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) {
53+
define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) nounwind {
54+
; CHECK-LABEL: selecti32_xcc:
55+
; CHECK: ! %bb.0: ! %entry
56+
; CHECK-NEXT: save %sp, -128, %sp
57+
; CHECK-NEXT: cmp %i0, %i1
58+
; CHECK-NEXT: movg %xcc, %i2, %i3
59+
; CHECK-NEXT: ret
60+
; CHECK-NEXT: restore %g0, %i3, %o0
4161
entry:
4262
%tobool = icmp sgt i64 %x, %y
4363
%rv = select i1 %tobool, i32 %a, i32 %b
4464
ret i32 %rv
4565
}
4666

47-
; CHECK: selecti64_xcc
48-
; CHECK: cmp %i0, %i1
49-
; CHECK: movg %xcc, %i2, %i3
50-
; CHECK: restore %g0, %i3, %o0
51-
define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) {
67+
define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) nounwind {
68+
; CHECK-LABEL: selecti64_xcc:
69+
; CHECK: ! %bb.0: ! %entry
70+
; CHECK-NEXT: save %sp, -128, %sp
71+
; CHECK-NEXT: cmp %i0, %i1
72+
; CHECK-NEXT: movg %xcc, %i2, %i3
73+
; CHECK-NEXT: ret
74+
; CHECK-NEXT: restore %g0, %i3, %o0
5275
entry:
5376
%tobool = icmp sgt i64 %x, %y
5477
%rv = select i1 %tobool, i64 %a, i64 %b
5578
ret i64 %rv
5679
}
5780

58-
; CHECK: selecti64_icc
59-
; CHECK: cmp %i0, %i1
60-
; CHECK: movg %icc, %i2, %i3
61-
; CHECK: restore %g0, %i3, %o0
62-
define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) {
81+
define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) nounwind {
82+
; CHECK-LABEL: selecti64_icc:
83+
; CHECK: ! %bb.0: ! %entry
84+
; CHECK-NEXT: save %sp, -128, %sp
85+
; CHECK-NEXT: cmp %i0, %i1
86+
; CHECK-NEXT: movg %icc, %i2, %i3
87+
; CHECK-NEXT: ret
88+
; CHECK-NEXT: restore %g0, %i3, %o0
6389
entry:
6490
%tobool = icmp sgt i32 %x, %y
6591
%rv = select i1 %tobool, i64 %a, i64 %b
6692
ret i64 %rv
6793
}
6894

69-
; CHECK: selecti64_fcc
70-
; CHECK: mov %i3, %i0
71-
; CHECK: fcmps %fcc0, %f1, %f3
72-
; CHECK: movul %fcc0, %i2, %i0
73-
; CHECK: restore
74-
define i64 @selecti64_fcc(float %x, float %y, i64 %a, i64 %b) {
95+
define i64 @selecti64_fcc(float %x, float %y, i64 %a, i64 %b) nounwind {
96+
; CHECK-LABEL: selecti64_fcc:
97+
; CHECK: ! %bb.0: ! %entry
98+
; CHECK-NEXT: save %sp, -128, %sp
99+
; CHECK-NEXT: mov %i3, %i0
100+
; CHECK-NEXT: fcmps %fcc0, %f1, %f3
101+
; CHECK-NEXT: movul %fcc0, %i2, %i0
102+
; CHECK-NEXT: ret
103+
; CHECK-NEXT: restore
75104
entry:
76105
%tobool = fcmp ult float %x, %y
77106
%rv = select i1 %tobool, i64 %a, i64 %b
78107
ret i64 %rv
79108
}
80109

81-
; CHECK: selectf32_xcc
82-
; CHECK: fmovs %f7, %f0
83-
; CHECK: cmp %i0, %i1
84-
; CHECK: fmovsg %xcc, %f5, %f0
85-
define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
110+
define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) nounwind {
111+
; CHECK-LABEL: selectf32_xcc:
112+
; CHECK: ! %bb.0: ! %entry
113+
; CHECK-NEXT: save %sp, -128, %sp
114+
; CHECK-NEXT: fmovs %f7, %f0
115+
; CHECK-NEXT: cmp %i0, %i1
116+
; CHECK-NEXT: fmovsg %xcc, %f5, %f0
117+
; CHECK-NEXT: ret
118+
; CHECK-NEXT: restore
86119
entry:
87120
%tobool = icmp sgt i64 %x, %y
88121
%rv = select i1 %tobool, float %a, float %b
89122
ret float %rv
90123
}
91124

92-
; CHECK: selectf64_xcc
93-
; CHECK: fmovd %f6, %f0
94-
; CHECK: cmp %i0, %i1
95-
; CHECK: fmovdg %xcc, %f4, %f0
96-
define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) {
125+
define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) nounwind {
126+
; CHECK-LABEL: selectf64_xcc:
127+
; CHECK: ! %bb.0: ! %entry
128+
; CHECK-NEXT: save %sp, -128, %sp
129+
; CHECK-NEXT: fmovd %f6, %f0
130+
; CHECK-NEXT: cmp %i0, %i1
131+
; CHECK-NEXT: fmovdg %xcc, %f4, %f0
132+
; CHECK-NEXT: ret
133+
; CHECK-NEXT: restore
97134
entry:
98135
%tobool = icmp sgt i64 %x, %y
99136
%rv = select i1 %tobool, double %a, double %b
100137
ret double %rv
101138
}
102139

103140
; The MOVXCC instruction can't use %g0 for its tied operand.
104-
; CHECK: select_consti64_xcc
105-
; CHECK: cmp
106-
; CHECK: movg %xcc, 123, %i{{[0-2]}}
107-
define i64 @select_consti64_xcc(i64 %x, i64 %y) {
141+
define i64 @select_consti64_xcc(i64 %x, i64 %y) nounwind {
142+
; CHECK-LABEL: select_consti64_xcc:
143+
; CHECK: ! %bb.0: ! %entry
144+
; CHECK-NEXT: save %sp, -128, %sp
145+
; CHECK-NEXT: mov %g0, %i2
146+
; CHECK-NEXT: cmp %i0, %i1
147+
; CHECK-NEXT: movg %xcc, 123, %i2
148+
; CHECK-NEXT: ret
149+
; CHECK-NEXT: restore %g0, %i2, %o0
108150
entry:
109151
%tobool = icmp sgt i64 %x, %y
110152
%rv = select i1 %tobool, i64 123, i64 0
111153
ret i64 %rv
112154
}
113155

114-
; CHECK-LABEL: setcc_resultty
115-
; CHECK-DAG: mov %g0, %o0
116-
; CHECK-DAG: mov %i0, %o1
117-
; CHECK-DAG: mov %g0, %o2
118-
; CHECK-DAG: mov 32, %o3
119-
; CHECK-DAG: call __multi3
120-
; CHECK: movrnz %o0, 1, [[R:%[gilo][0-7]]]
121-
; CHECK: or [[R]], %i1, %i0
122-
123-
define i1 @setcc_resultty(i64 %a, i1 %b) {
156+
define i1 @setcc_resultty(i64 %a, i1 %b) nounwind {
157+
; CHECK-LABEL: setcc_resultty:
158+
; CHECK: ! %bb.0:
159+
; CHECK-NEXT: save %sp, -128, %sp
160+
; CHECK-NEXT: mov %g0, %i2
161+
; CHECK-NEXT: sethi 4194303, %i3
162+
; CHECK-NEXT: or %i3, 1023, %i3
163+
; CHECK-NEXT: sethi 131071, %i4
164+
; CHECK-NEXT: or %i4, 1023, %i4
165+
; CHECK-NEXT: sllx %i4, 32, %i4
166+
; CHECK-NEXT: or %i4, %i3, %i3
167+
; CHECK-NEXT: and %i0, %i3, %i3
168+
; CHECK-NEXT: cmp %i3, %i0
169+
; CHECK-NEXT: movne %xcc, 1, %i2
170+
; CHECK-NEXT: or %i2, %i1, %i0
171+
; CHECK-NEXT: ret
172+
; CHECK-NEXT: restore
124173
%a0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 32)
125174
%a1 = extractvalue { i64, i1 } %a0, 1
126175
%a4 = or i1 %a1, %b

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