[Sparc] Remove custom lowering for SMULO / UMULO #100858
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The underlying issue was fixed by 7c4fe0e. The lowering is tested by [us]mulo-128-legalisation-lowering.ll and there are no changes.
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@llvm/pr-subscribers-backend-sparc Author: Sergei Barannikov (s-barannikov) ChangesThe underlying issue was fixed by 7c4fe0e. The lowering is tested by Full diff: https://github.com/llvm/llvm-project/pull/100858.diff 2 Files Affected:
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 50aa19446f880..2f72165814ffa 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1855,9 +1855,6 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::MULHU, MVT::i64, Expand);
setOperationAction(ISD::MULHS, MVT::i64, Expand);
- setOperationAction(ISD::UMULO, MVT::i64, Custom);
- setOperationAction(ISD::SMULO, MVT::i64, Custom);
-
setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
@@ -3154,61 +3151,6 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
return DAG.getMergeValues(Ops, dl);
}
-// Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
-// in LegalizeDAG.cpp except the order of arguments to the library function.
-static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
- const SparcTargetLowering &TLI)
-{
- unsigned opcode = Op.getOpcode();
- assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
-
- bool isSigned = (opcode == ISD::SMULO);
- EVT VT = MVT::i64;
- EVT WideVT = MVT::i128;
- SDLoc dl(Op);
- SDValue LHS = Op.getOperand(0);
-
- if (LHS.getValueType() != VT)
- return Op;
-
- SDValue ShiftAmt = DAG.getConstant(63, dl, VT);
-
- SDValue RHS = Op.getOperand(1);
- SDValue HiLHS, HiRHS;
- if (isSigned) {
- HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
- HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
- } else {
- HiLHS = DAG.getConstant(0, dl, VT);
- HiRHS = DAG.getConstant(0, dl, MVT::i64);
- }
-
- SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
-
- TargetLowering::MakeLibCallOptions CallOptions;
- CallOptions.setSExt(isSigned);
- SDValue MulResult = TLI.makeLibCall(DAG,
- RTLIB::MUL_I128, WideVT,
- Args, CallOptions, dl).first;
- SDValue BottomHalf, TopHalf;
- std::tie(BottomHalf, TopHalf) = DAG.SplitScalar(MulResult, dl, VT, VT);
- if (isSigned) {
- SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
- TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
- } else {
- TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT),
- ISD::SETNE);
- }
- // MulResult is a node with an illegal type. Because such things are not
- // generally permitted during this phase of legalization, ensure that
- // nothing is left using the node. The above EXTRACT_ELEMENT nodes should have
- // been folded.
- assert(MulResult->use_empty() && "Illegally typed node still in use!");
-
- SDValue Ops[2] = { BottomHalf, TopHalf } ;
- return DAG.getMergeValues(Ops, dl);
-}
-
static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
if (isStrongerThanMonotonic(cast<AtomicSDNode>(Op)->getSuccessOrdering())) {
// Expand with a fence.
@@ -3287,8 +3229,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::ADDE:
case ISD::SUBC:
case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
- case ISD::UMULO:
- case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
case ISD::ATOMIC_LOAD:
case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
diff --git a/llvm/test/CodeGen/SPARC/64cond.ll b/llvm/test/CodeGen/SPARC/64cond.ll
index 10d070055a4ec..5a90022004664 100644
--- a/llvm/test/CodeGen/SPARC/64cond.ll
+++ b/llvm/test/CodeGen/SPARC/64cond.ll
@@ -1,10 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=sparc64-pc-openbsd -disable-sparc-leaf-proc | FileCheck %s
; Testing 64-bit conditionals. The sparc64 triple is an alias for sparcv9.
-; CHECK: cmpri
-; CHECK: cmp %i1, 1
-; CHECK: be %xcc,
-define void @cmpri(ptr %p, i64 %x) {
+define void @cmpri(ptr %p, i64 %x) nounwind {
+; CHECK-LABEL: cmpri:
+; CHECK: ! %bb.0: ! %entry
+; CHECK-NEXT: save %sp, -128, %sp
+; CHECK-NEXT: cmp %i1, 1
+; CHECK-NEXT: be %xcc, .LBB0_2
+; CHECK-NEXT: nop
+; CHECK-NEXT: ! %bb.1: ! %if.then
+; CHECK-NEXT: stx %i1, [%i0]
+; CHECK-NEXT: .LBB0_2: ! %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: restore
entry:
%tobool = icmp eq i64 %x, 1
br i1 %tobool, label %if.end, label %if.then
@@ -17,10 +26,18 @@ if.end:
ret void
}
-; CHECK: cmprr
-; CHECK: cmp %i1, %i2
-; CHECK: bgu %xcc,
-define void @cmprr(ptr %p, i64 %x, i64 %y) {
+define void @cmprr(ptr %p, i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: cmprr:
+; CHECK: ! %bb.0: ! %entry
+; CHECK-NEXT: save %sp, -128, %sp
+; CHECK-NEXT: cmp %i1, %i2
+; CHECK-NEXT: bgu %xcc, .LBB1_2
+; CHECK-NEXT: nop
+; CHECK-NEXT: ! %bb.1: ! %if.then
+; CHECK-NEXT: stx %i1, [%i0]
+; CHECK-NEXT: .LBB1_2: ! %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: restore
entry:
%tobool = icmp ugt i64 %x, %y
br i1 %tobool, label %if.end, label %if.then
@@ -33,67 +50,87 @@ if.end:
ret void
}
-; CHECK: selecti32_xcc
-; CHECK: cmp %i0, %i1
-; CHECK: movg %xcc, %i2, %i3
-; CHECK: restore %g0, %i3, %o0
-define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) {
+define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: selecti32_xcc:
+; CHECK: ! %bb.0: ! %entry
+; CHECK-NEXT: save %sp, -128, %sp
+; CHECK-NEXT: cmp %i0, %i1
+; CHECK-NEXT: movg %xcc, %i2, %i3
+; CHECK-NEXT: ret
+; CHECK-NEXT: restore %g0, %i3, %o0
entry:
%tobool = icmp sgt i64 %x, %y
%rv = select i1 %tobool, i32 %a, i32 %b
ret i32 %rv
}
-; CHECK: selecti64_xcc
-; CHECK: cmp %i0, %i1
-; CHECK: movg %xcc, %i2, %i3
-; CHECK: restore %g0, %i3, %o0
-define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) {
+define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: selecti64_xcc:
+; CHECK: ! %bb.0: ! %entry
+; CHECK-NEXT: save %sp, -128, %sp
+; CHECK-NEXT: cmp %i0, %i1
+; CHECK-NEXT: movg %xcc, %i2, %i3
+; CHECK-NEXT: ret
+; CHECK-NEXT: restore %g0, %i3, %o0
entry:
%tobool = icmp sgt i64 %x, %y
%rv = select i1 %tobool, i64 %a, i64 %b
ret i64 %rv
}
-; CHECK: selecti64_icc
-; CHECK: cmp %i0, %i1
-; CHECK: movg %icc, %i2, %i3
-; CHECK: restore %g0, %i3, %o0
-define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) {
+define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: selecti64_icc:
+; CHECK: ! %bb.0: ! %entry
+; CHECK-NEXT: save %sp, -128, %sp
+; CHECK-NEXT: cmp %i0, %i1
+; CHECK-NEXT: movg %icc, %i2, %i3
+; CHECK-NEXT: ret
+; CHECK-NEXT: restore %g0, %i3, %o0
entry:
%tobool = icmp sgt i32 %x, %y
%rv = select i1 %tobool, i64 %a, i64 %b
ret i64 %rv
}
-; CHECK: selecti64_fcc
-; CHECK: mov %i3, %i0
-; CHECK: fcmps %fcc0, %f1, %f3
-; CHECK: movul %fcc0, %i2, %i0
-; CHECK: restore
-define i64 @selecti64_fcc(float %x, float %y, i64 %a, i64 %b) {
+define i64 @selecti64_fcc(float %x, float %y, i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: selecti64_fcc:
+; CHECK: ! %bb.0: ! %entry
+; CHECK-NEXT: save %sp, -128, %sp
+; CHECK-NEXT: mov %i3, %i0
+; CHECK-NEXT: fcmps %fcc0, %f1, %f3
+; CHECK-NEXT: movul %fcc0, %i2, %i0
+; CHECK-NEXT: ret
+; CHECK-NEXT: restore
entry:
%tobool = fcmp ult float %x, %y
%rv = select i1 %tobool, i64 %a, i64 %b
ret i64 %rv
}
-; CHECK: selectf32_xcc
-; CHECK: fmovs %f7, %f0
-; CHECK: cmp %i0, %i1
-; CHECK: fmovsg %xcc, %f5, %f0
-define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
+define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) nounwind {
+; CHECK-LABEL: selectf32_xcc:
+; CHECK: ! %bb.0: ! %entry
+; CHECK-NEXT: save %sp, -128, %sp
+; CHECK-NEXT: fmovs %f7, %f0
+; CHECK-NEXT: cmp %i0, %i1
+; CHECK-NEXT: fmovsg %xcc, %f5, %f0
+; CHECK-NEXT: ret
+; CHECK-NEXT: restore
entry:
%tobool = icmp sgt i64 %x, %y
%rv = select i1 %tobool, float %a, float %b
ret float %rv
}
-; CHECK: selectf64_xcc
-; CHECK: fmovd %f6, %f0
-; CHECK: cmp %i0, %i1
-; CHECK: fmovdg %xcc, %f4, %f0
-define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) {
+define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) nounwind {
+; CHECK-LABEL: selectf64_xcc:
+; CHECK: ! %bb.0: ! %entry
+; CHECK-NEXT: save %sp, -128, %sp
+; CHECK-NEXT: fmovd %f6, %f0
+; CHECK-NEXT: cmp %i0, %i1
+; CHECK-NEXT: fmovdg %xcc, %f4, %f0
+; CHECK-NEXT: ret
+; CHECK-NEXT: restore
entry:
%tobool = icmp sgt i64 %x, %y
%rv = select i1 %tobool, double %a, double %b
@@ -101,26 +138,38 @@ entry:
}
; The MOVXCC instruction can't use %g0 for its tied operand.
-; CHECK: select_consti64_xcc
-; CHECK: cmp
-; CHECK: movg %xcc, 123, %i{{[0-2]}}
-define i64 @select_consti64_xcc(i64 %x, i64 %y) {
+define i64 @select_consti64_xcc(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: select_consti64_xcc:
+; CHECK: ! %bb.0: ! %entry
+; CHECK-NEXT: save %sp, -128, %sp
+; CHECK-NEXT: mov %g0, %i2
+; CHECK-NEXT: cmp %i0, %i1
+; CHECK-NEXT: movg %xcc, 123, %i2
+; CHECK-NEXT: ret
+; CHECK-NEXT: restore %g0, %i2, %o0
entry:
%tobool = icmp sgt i64 %x, %y
%rv = select i1 %tobool, i64 123, i64 0
ret i64 %rv
}
-; CHECK-LABEL: setcc_resultty
-; CHECK-DAG: mov %g0, %o0
-; CHECK-DAG: mov %i0, %o1
-; CHECK-DAG: mov %g0, %o2
-; CHECK-DAG: mov 32, %o3
-; CHECK-DAG: call __multi3
-; CHECK: movrnz %o0, 1, [[R:%[gilo][0-7]]]
-; CHECK: or [[R]], %i1, %i0
-
-define i1 @setcc_resultty(i64 %a, i1 %b) {
+define i1 @setcc_resultty(i64 %a, i1 %b) nounwind {
+; CHECK-LABEL: setcc_resultty:
+; CHECK: ! %bb.0:
+; CHECK-NEXT: save %sp, -128, %sp
+; CHECK-NEXT: mov %g0, %i2
+; CHECK-NEXT: sethi 4194303, %i3
+; CHECK-NEXT: or %i3, 1023, %i3
+; CHECK-NEXT: sethi 131071, %i4
+; CHECK-NEXT: or %i4, 1023, %i4
+; CHECK-NEXT: sllx %i4, 32, %i4
+; CHECK-NEXT: or %i4, %i3, %i3
+; CHECK-NEXT: and %i0, %i3, %i3
+; CHECK-NEXT: cmp %i3, %i0
+; CHECK-NEXT: movne %xcc, 1, %i2
+; CHECK-NEXT: or %i2, %i1, %i0
+; CHECK-NEXT: ret
+; CHECK-NEXT: restore
%a0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 32)
%a1 = extractvalue { i64, i1 } %a0, 1
%a4 = or i1 %a1, %b
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You can test this locally with the following command:git-clang-format --diff fe07d9aa410518c5b631a065ddc5782a623af030 8a28e9df4b90d5d4d3fa08f2af88c6a71eed1116 --extensions cpp -- llvm/lib/Target/Sparc/SparcISelLowering.cppView the diff from clang-format here.diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 2f72165814..e20a414d0f 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -3228,7 +3228,8 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::ADDC:
case ISD::ADDE:
case ISD::SUBC:
- case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
+ case ISD::SUBE:
+ return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
case ISD::ATOMIC_LOAD:
case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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The underlying issue was fixed by 7c4fe0e. The lowering is tested by
[us]mulo-128-legalisation-lowering.ll and there are no changes.