[ARM] Fix pointer offset when splitting stores from VMOVDRR

We were not accounting for the pointer offset when splitting a store from
a VMOVDRR node, which could lead to incorrect aliasing info. In this
case it is the fneg via integer arithmetic that gives us a store->load
pair that we started getting wrong.

Differential Revision: https://reviews.llvm.org/D88653

Author: davemgreen

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -14546,15 +14546,15 @@ static SDValue PerformSTORECombine(SDNode *N,
     SDValue BasePtr = St->getBasePtr();
     SDValue NewST1 = DAG.getStore(
         St->getChain(), DL, StVal.getNode()->getOperand(isBigEndian ? 1 : 0),
-        BasePtr, St->getPointerInfo(), St->getAlignment(),
+        BasePtr, St->getPointerInfo(), St->getOriginalAlign(),
         St->getMemOperand()->getFlags());
 
     SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
                                     DAG.getConstant(4, DL, MVT::i32));
     return DAG.getStore(NewST1.getValue(0), DL,
                         StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
-                        OffsetPtr, St->getPointerInfo(),
-                        std::min(4U, St->getAlignment() / 2),
+                        OffsetPtr, St->getPointerInfo().getWithOffset(4),
+                        St->getOriginalAlign(),
                         St->getMemOperand()->getFlags());
   }
 

llvm/test/CodeGen/Thumb2/vmovdrroffset.ll

@@ -21,9 +21,9 @@ define arm_aapcs_vfpcc double @zero(double %a, double %b, double %c) {
 ; CHECK-NEXT:    vmov r2, r3, d8
 ; CHECK-NEXT:    vmov r0, r1, d0
 ; CHECK-NEXT:    bl __aeabi_dadd
+; CHECK-NEXT:    str r1, [sp, #4]
 ; CHECK-NEXT:    mov r4, r0
 ; CHECK-NEXT:    ldrb.w r0, [sp, #7]
-; CHECK-NEXT:    str r1, [sp, #4]
 ; CHECK-NEXT:    eor r0, r0, #128
 ; CHECK-NEXT:    strb.w r0, [sp, #7]
 ; CHECK-NEXT:    vmov r0, r1, d9