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Feedback, decapitalize methods, stringref in unittest where possible, remove redundant inline
1 parent b8234b2 commit 82d7d36

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5 files changed

+86
-86
lines changed

5 files changed

+86
-86
lines changed

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUDelayedMCExpr.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ static msgpack::DocNode getNode(msgpack::DocNode DN, msgpack::Type Type,
2727
}
2828
}
2929

30-
void DelayedMCExpr::AssignDocNode(msgpack::DocNode &DN, msgpack::Type Type,
30+
void DelayedMCExpr::assignDocNode(msgpack::DocNode &DN, msgpack::Type Type,
3131
const MCExpr *Expr) {
3232
MCValue Res;
3333
if (Expr->evaluateAsRelocatable(Res, nullptr, nullptr)) {
@@ -40,7 +40,7 @@ void DelayedMCExpr::AssignDocNode(msgpack::DocNode &DN, msgpack::Type Type,
4040
DelayedExprs.push_back(DelayedExpr{DN, Type, Expr});
4141
}
4242

43-
bool DelayedMCExpr::ResolveDelayedExpressions() {
43+
bool DelayedMCExpr::resolveDelayedExpressions() {
4444
bool Success;
4545

4646
while (!DelayedExprs.empty()) {

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUDelayedMCExpr.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,8 +27,8 @@ class DelayedMCExpr {
2727
std::deque<DelayedExpr> DelayedExprs;
2828

2929
public:
30-
bool ResolveDelayedExpressions();
31-
void AssignDocNode(msgpack::DocNode &DN, msgpack::Type Type,
30+
bool resolveDelayedExpressions();
31+
void assignDocNode(msgpack::DocNode &DN, msgpack::Type Type,
3232
const MCExpr *Expr);
3333
void clear();
3434
bool empty();

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -224,7 +224,7 @@ void AMDGPUPALMetadata::setRegister(unsigned Reg, const MCExpr *Val,
224224
REM[Reg] = Val;
225225
(void)Unused;
226226
}
227-
DelayedExprs.AssignDocNode(N, msgpack::Type::UInt, Val);
227+
DelayedExprs.assignDocNode(N, msgpack::Type::UInt, Val);
228228
}
229229

230230
// Set the entry point name for one shader.
@@ -350,7 +350,7 @@ void AMDGPUPALMetadata::setFunctionNumUsedVgprs(StringRef FnName,
350350
void AMDGPUPALMetadata::setFunctionNumUsedVgprs(StringRef FnName,
351351
const MCExpr *Val) {
352352
auto Node = getShaderFunction(FnName);
353-
DelayedExprs.AssignDocNode(Node[".vgpr_count"], msgpack::Type::UInt, Val);
353+
DelayedExprs.assignDocNode(Node[".vgpr_count"], msgpack::Type::UInt, Val);
354354
}
355355

356356
// Set the number of used vgprs in the metadata.
@@ -363,7 +363,7 @@ void AMDGPUPALMetadata::setFunctionNumUsedSgprs(StringRef FnName,
363363
void AMDGPUPALMetadata::setFunctionNumUsedSgprs(StringRef FnName,
364364
const MCExpr *Val) {
365365
auto Node = getShaderFunction(FnName);
366-
DelayedExprs.AssignDocNode(Node[".sgpr_count"], msgpack::Type::UInt, Val);
366+
DelayedExprs.assignDocNode(Node[".sgpr_count"], msgpack::Type::UInt, Val);
367367
}
368368

369369
// Set the hardware register bit in PAL metadata to enable wave32 on the
@@ -762,7 +762,7 @@ void AMDGPUPALMetadata::toString(std::string &String) {
762762
String.clear();
763763
if (!BlobType)
764764
return;
765-
ResolvedAll = DelayedExprs.ResolveDelayedExpressions();
765+
ResolvedAll = DelayedExprs.resolveDelayedExpressions();
766766
raw_string_ostream Stream(String);
767767
if (isLegacy()) {
768768
if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil)
@@ -812,7 +812,7 @@ void AMDGPUPALMetadata::toString(std::string &String) {
812812
// a .note record of the specified AMD type. Returns an empty blob if
813813
// there is no PAL metadata,
814814
void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) {
815-
ResolvedAll = DelayedExprs.ResolveDelayedExpressions();
815+
ResolvedAll = DelayedExprs.resolveDelayedExpressions();
816816
if (Type == ELF::NT_AMD_PAL_METADATA)
817817
toLegacyBlob(Blob);
818818
else if (Type)
@@ -1052,7 +1052,7 @@ void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, bool Val) {
10521052

10531053
void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field,
10541054
msgpack::Type Type, const MCExpr *Val) {
1055-
DelayedExprs.AssignDocNode(getHwStage(CC)[field], Type, Val);
1055+
DelayedExprs.assignDocNode(getHwStage(CC)[field], Type, Val);
10561056
}
10571057

10581058
void AMDGPUPALMetadata::setComputeRegisters(StringRef field, unsigned Val) {

‎llvm/lib/Target/AMDGPU/Utils/SIDefinesUtils.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ namespace AMDGPU {
2424
///
2525
/// For example, given C_00B848_FWD_PROGRESS (i.e., 0x7FFFFFFF) from
2626
/// SIDefines.h, this will return the pair as (31,1).
27-
constexpr inline std::pair<unsigned, unsigned> getShiftMask(unsigned Value) {
27+
constexpr std::pair<unsigned, unsigned> getShiftMask(unsigned Value) {
2828
unsigned Shift = 0;
2929
unsigned Mask = 0;
3030

‎llvm/unittests/Target/AMDGPU/PALMetadata.cpp

Lines changed: 75 additions & 75 deletions
Original file line numberDiff line numberDiff line change
@@ -40,9 +40,9 @@ class PALMetadata : public testing::Test {
4040
}
4141

4242
PALMetadata() {
43-
std::string Triple = "amdgcn--amdpal";
44-
std::string CPU = "gfx1010";
45-
std::string FS = "";
43+
StringRef Triple = "amdgcn--amdpal";
44+
StringRef CPU = "gfx1010";
45+
StringRef FS = "";
4646

4747
std::string Error;
4848
const Target *TheTarget = TargetRegistry::lookupTarget(Triple, Error);
@@ -67,18 +67,18 @@ class PALMetadata : public testing::Test {
6767
};
6868

6969
TEST_F(PALMetadata, ResourceRegisterSetORsResolvableUnknown) {
70-
std::string yaml = "---\n"
71-
"amdpal.pipelines:\n"
72-
" - .hardware_stages:\n"
73-
" .es:\n"
74-
" .entry_point: Test\n"
75-
" .scratch_memory_size: 0\n"
76-
" .sgpr_count: 0x1\n"
77-
" .vgpr_count: 0x1\n"
78-
" .registers:\n"
79-
" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
80-
" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
81-
"...\n";
70+
StringRef yaml = "---\n"
71+
"amdpal.pipelines:\n"
72+
" - .hardware_stages:\n"
73+
" .es:\n"
74+
" .entry_point: Test\n"
75+
" .scratch_memory_size: 0\n"
76+
" .sgpr_count: 0x1\n"
77+
" .vgpr_count: 0x1\n"
78+
" .registers:\n"
79+
" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
80+
" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
81+
"...\n";
8282

8383
MCContext &MCCtx = MF->getContext();
8484
auto CC = CallingConv::AMDGPU_VS;
@@ -100,18 +100,18 @@ TEST_F(PALMetadata, ResourceRegisterSetORsResolvableUnknown) {
100100
}
101101

102102
TEST_F(PALMetadata, ResourceRegisterSetORsResolvableUnknowns) {
103-
std::string yaml = "---\n"
104-
"amdpal.pipelines:\n"
105-
" - .hardware_stages:\n"
106-
" .es:\n"
107-
" .entry_point: Test\n"
108-
" .scratch_memory_size: 0\n"
109-
" .sgpr_count: 0x1\n"
110-
" .vgpr_count: 0x1\n"
111-
" .registers:\n"
112-
" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
113-
" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
114-
"...\n";
103+
StringRef yaml = "---\n"
104+
"amdpal.pipelines:\n"
105+
" - .hardware_stages:\n"
106+
" .es:\n"
107+
" .entry_point: Test\n"
108+
" .scratch_memory_size: 0\n"
109+
" .sgpr_count: 0x1\n"
110+
" .vgpr_count: 0x1\n"
111+
" .registers:\n"
112+
" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
113+
" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
114+
"...\n";
115115

116116
MCContext &MCCtx = MF->getContext();
117117
auto CC = CallingConv::AMDGPU_VS;
@@ -138,18 +138,18 @@ TEST_F(PALMetadata, ResourceRegisterSetORsResolvableUnknowns) {
138138
}
139139

140140
TEST_F(PALMetadata, ResourceRegisterSetORsPreset) {
141-
std::string yaml = "---\n"
142-
"amdpal.pipelines:\n"
143-
" - .hardware_stages:\n"
144-
" .es:\n"
145-
" .entry_point: Test\n"
146-
" .scratch_memory_size: 0\n"
147-
" .sgpr_count: 0x1\n"
148-
" .vgpr_count: 0x1\n"
149-
" .registers:\n"
150-
" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
151-
" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0x2a\n"
152-
"...\n";
141+
StringRef yaml = "---\n"
142+
"amdpal.pipelines:\n"
143+
" - .hardware_stages:\n"
144+
" .es:\n"
145+
" .entry_point: Test\n"
146+
" .scratch_memory_size: 0\n"
147+
" .sgpr_count: 0x1\n"
148+
" .vgpr_count: 0x1\n"
149+
" .registers:\n"
150+
" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
151+
" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0x2a\n"
152+
"...\n";
153153

154154
MCContext &MCCtx = MF->getContext();
155155
auto CC = CallingConv::AMDGPU_VS;
@@ -166,18 +166,18 @@ TEST_F(PALMetadata, ResourceRegisterSetORsPreset) {
166166
}
167167

168168
TEST_F(PALMetadata, ResourceRegisterSetORs) {
169-
std::string yaml = "---\n"
170-
"amdpal.pipelines:\n"
171-
" - .hardware_stages:\n"
172-
" .es:\n"
173-
" .entry_point: Test\n"
174-
" .scratch_memory_size: 0\n"
175-
" .sgpr_count: 0x1\n"
176-
" .vgpr_count: 0x1\n"
177-
" .registers:\n"
178-
" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
179-
" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
180-
"...\n";
169+
StringRef yaml = "---\n"
170+
"amdpal.pipelines:\n"
171+
" - .hardware_stages:\n"
172+
" .es:\n"
173+
" .entry_point: Test\n"
174+
" .scratch_memory_size: 0\n"
175+
" .sgpr_count: 0x1\n"
176+
" .vgpr_count: 0x1\n"
177+
" .registers:\n"
178+
" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
179+
" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
180+
"...\n";
181181

182182
MCContext &MCCtx = MF->getContext();
183183
auto CC = CallingConv::AMDGPU_VS;
@@ -195,18 +195,18 @@ TEST_F(PALMetadata, ResourceRegisterSetORs) {
195195
}
196196

197197
TEST_F(PALMetadata, ResourceRegisterSetUnresolvedSym) {
198-
std::string yaml = "---\n"
199-
"amdpal.pipelines:\n"
200-
" - .hardware_stages:\n"
201-
" .es:\n"
202-
" .entry_point: Test\n"
203-
" .scratch_memory_size: 0\n"
204-
" .sgpr_count: 0x1\n"
205-
" .vgpr_count: 0x1\n"
206-
" .registers:\n"
207-
" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
208-
" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
209-
"...\n";
198+
StringRef yaml = "---\n"
199+
"amdpal.pipelines:\n"
200+
" - .hardware_stages:\n"
201+
" .es:\n"
202+
" .entry_point: Test\n"
203+
" .scratch_memory_size: 0\n"
204+
" .sgpr_count: 0x1\n"
205+
" .vgpr_count: 0x1\n"
206+
" .registers:\n"
207+
" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
208+
" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
209+
"...\n";
210210

211211
MCContext &MCCtx = MF->getContext();
212212
auto CC = CallingConv::AMDGPU_VS;
@@ -221,18 +221,18 @@ TEST_F(PALMetadata, ResourceRegisterSetUnresolvedSym) {
221221
}
222222

223223
TEST_F(PALMetadata, ResourceRegisterSetNoEmitUnresolved) {
224-
std::string yaml = "---\n"
225-
"amdpal.pipelines:\n"
226-
" - .hardware_stages:\n"
227-
" .es:\n"
228-
" .entry_point: Test\n"
229-
" .scratch_memory_size: 0\n"
230-
" .sgpr_count: 0x1\n"
231-
" .vgpr_count: 0x1\n"
232-
" .registers:\n"
233-
" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
234-
" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
235-
"...\n";
224+
StringRef yaml = "---\n"
225+
"amdpal.pipelines:\n"
226+
" - .hardware_stages:\n"
227+
" .es:\n"
228+
" .entry_point: Test\n"
229+
" .scratch_memory_size: 0\n"
230+
" .sgpr_count: 0x1\n"
231+
" .vgpr_count: 0x1\n"
232+
" .registers:\n"
233+
" \'0x2c4a (SPI_SHADER_PGM_RSRC1_VS)\': 0x2f0000\n"
234+
" \'0x2c4b (SPI_SHADER_PGM_RSRC2_VS)\': 0\n"
235+
"...\n";
236236

237237
MCContext &MCCtx = MF->getContext();
238238
auto CC = CallingConv::AMDGPU_VS;

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